Difference between revisions of "X86 microop ISA"

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</table>
 
</table>
  
−
==== Adc ====
+
== Adc ==
 +
=== adc: Dest = Src1 + Src2 + CF ===
 +
Adds the contents of the Src1 and Src2 registers and the carry flag and puts the result in the Dest register.
  
−
==== Sub ====
+
=== adci: Dest = Src1 + Imm + CF ===
 +
Adds the contents of the Src1 register, the immediate Imm, and the carry flag and puts the result in the Dest register.
  
−
==== Sbb ====
+
=== Flags ===
 +
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.
  
−
=== Multiplication and division ===
+
<table>
 +
  <tr>
 +
    <td> <b>CF and ECF</b> </td><td>The carry out of the most significant bit.</td>
 +
  </tr>
 +
  <tr>
 +
    <td> <b>ZF and EZF</b> </td><td>Whether the result was zero.</td>
 +
  </tr>
 +
  <tr>
 +
    <td> <b>PF</b> </td><td> The parity of the result. </td>
 +
  </tr>
 +
  <tr>
 +
    <td> <b>AF</b> </td><td> The carry from the 4th to 5th bit positions. </td>
 +
  </tr>
 +
  <tr>
 +
    <td> <b>SF</b> </td><td> The sign of the result. </td>
 +
  </tr>
 +
  <tr>
 +
    <td> <b>OF</b> </td><td> Whether there was an overflow. </td>
 +
  </tr>
 +
</table>
  
−
==== Mul1s ====
+
== Sub ==
  
−
==== Mul1u ====
+
== Sbb ==
  
−
==== Mulel ====
+
== Mul1s ==
  
−
==== Muleh ====
+
== Mul1u ==
  
−
==== Div1 ====
+
== Mulel ==
  
−
==== Div2 ====
+
== Muleh ==
  
−
==== Divq ====
+
== Div1 ==
  
−
==== Divr ====
+
== Div2 ==
  
−
=== Logic ===
+
== Divq ==
  
−
==== Or ====
+
== Divr ==
  
−
==== And ====
+
== Or ==
  
−
==== Xor ====
+
== And ==
  
−
=== Shifts and Rotates ===
+
== Xor ==
  
−
==== Sll ====
+
== Sll ==
  
−
==== Srl ====
+
== Srl ==
  
−
==== Sra ====
+
== Sra ==
  
−
==== Ror ====
+
== Ror ==
  
−
==== Rcr ====
+
== Rcr ==
  
−
==== Rol ====
+
== Rol ==
  
−
==== Rcl ====
+
== Rcl ==
  
−
=== Data transfer and conversion ===
+
== Mov ==
  
−
==== Mov ====
+
== Sext ==
  
−
==== Sext ====
+
== Zext ==
  
−
==== Zext ====
+
== Ruflag ==
  
−
==== Ruflag ====
+
== Ruflags ==
  
−
==== Ruflags ====
+
== Wruflags ==
  
−
==== Wruflags ====
+
== Br ==
  
−
=== Control transfer ===
+
== Rdip ==
  
−
==== Br ====
+
== Wrip ==
  
−
==== Rdip ====
+
= Load/Store Ops =
  
−
==== Wrip ====
+
= Load immediate Op =
−
 
 
−
== Load/Store Ops ==
 
−
 
 
−
== Load immediate Op ==
 

Revision as of 14:58, 27 September 2007

Register Ops

Add

add: Dest = Src1 + Src2

Adds the contents of the Src1 and Src2 registers and puts the result in the Dest register.

addi: Dest = Src1 + Imm

Adds the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF The carry out of the most significant bit.
ZF and EZF Whether the result was zero.
PF The parity of the result.
AF The carry from the 4th to 5th bit positions.
SF The sign of the result.
OF Whether there was an overflow.

Adc

adc: Dest = Src1 + Src2 + CF

Adds the contents of the Src1 and Src2 registers and the carry flag and puts the result in the Dest register.

adci: Dest = Src1 + Imm + CF

Adds the contents of the Src1 register, the immediate Imm, and the carry flag and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF The carry out of the most significant bit.
ZF and EZF Whether the result was zero.
PF The parity of the result.
AF The carry from the 4th to 5th bit positions.
SF The sign of the result.
OF Whether there was an overflow.

Sub

Sbb

Mul1s

Mul1u

Mulel

Muleh

Div1

Div2

Divq

Divr

Or

And

Xor

Sll

Srl

Sra

Ror

Rcr

Rol

Rcl

Mov

Sext

Zext

Ruflag

Ruflags

Wruflags

Br

Rdip

Wrip

Load/Store Ops

Load immediate Op

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