Difference between revisions of "X86 microop ISA"

From gem5
Jump to: navigation, search
Line 2: Line 2:
  
 
== Add ==
 
== Add ==
 +
Addition.
 +
 
=== add Dest, Src1, Src2 ===
 
=== add Dest, Src1, Src2 ===
−
Dest = Src1 + Src2
+
Dest = Dest <- Src1 + Src2
  
 
Adds the contents of the Src1 and Src2 registers and puts the result in the Dest register.
 
Adds the contents of the Src1 and Src2 registers and puts the result in the Dest register.
  
 
=== addi Dest, Src1, Imm ===
 
=== addi Dest, Src1, Imm ===
−
Dest = Src1 + Imm
+
Dest = Dest <- Src1 + Imm
  
 
Adds the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
 
Adds the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
Line 37: Line 39:
  
 
== Adc ==
 
== Adc ==
 +
 +
Add with carry.
 +
 
=== adc Dest, Src1, Src2 ===
 
=== adc Dest, Src1, Src2 ===
−
Dest = Src1 + Src2 + CF
+
Dest = Dest <- Src1 + Src2 + CF
  
 
Adds the contents of the Src1 and Src2 registers and the carry flag and puts the result in the Dest register.
 
Adds the contents of the Src1 and Src2 registers and the carry flag and puts the result in the Dest register.
  
 
=== adci Dest, Src1, Imm ===
 
=== adci Dest, Src1, Imm ===
−
Dest = Src1 + Imm + CF
+
Dest = Dest <- Src1 + Imm + CF
  
 
Adds the contents of the Src1 register, the immediate Imm, and the carry flag and puts the result in the Dest register.
 
Adds the contents of the Src1 register, the immediate Imm, and the carry flag and puts the result in the Dest register.
Line 72: Line 77:
  
 
== Sub ==
 
== Sub ==
 +
 +
Subtraction.
  
 
=== sub Dest, Src1, Src2 ===
 
=== sub Dest, Src1, Src2 ===
−
Dest = Src1 - Src2
+
Dest = Dest <- Src1 - Src2
  
 
Subtracts the contents of the Src2 register from the Src1 register and puts the result in the Dest register.
 
Subtracts the contents of the Src2 register from the Src1 register and puts the result in the Dest register.
  
 
=== subi Dest, Src1, Imm ===
 
=== subi Dest, Src1, Imm ===
−
Dest = Src1 - Imm
+
Dest = Dest <- Src1 - Imm
  
 
Subtracts the contents of the immediate Imm from the Src1 register and puts the result in the Dest register.
 
Subtracts the contents of the immediate Imm from the Src1 register and puts the result in the Dest register.
Line 108: Line 115:
  
 
== Sbb ==
 
== Sbb ==
 +
 +
Subtract with barrow.
  
 
=== sbb Dest, Src1, Src2 ===
 
=== sbb Dest, Src1, Src2 ===
−
Dest = Src1 - Src2 - CF
+
Dest = Dest <- Src1 - Src2 - CF
  
 
Subtracts the contents of the Src2 register and the carry flag from the Src1 register and puts the result in the Dest register.
 
Subtracts the contents of the Src2 register and the carry flag from the Src1 register and puts the result in the Dest register.
  
 
=== sbbi Dest, Src1, Imm ===
 
=== sbbi Dest, Src1, Imm ===
−
Dest = Src1 - Imm - CF
+
Dest = Dest <- Src1 - Imm - CF
  
 
Subtracts the immediate Imm and the carry flag from the Src1 register and puts the result in the Dest register.
 
Subtracts the immediate Imm and the carry flag from the Src1 register and puts the result in the Dest register.
Line 144: Line 153:
  
 
== Mul1s ==
 
== Mul1s ==
 +
 +
Signed multiply.
  
 
=== mul1s Src1, Src2 ===
 
=== mul1s Src1, Src2 ===
Line 159: Line 170:
  
 
== Mul1u ==
 
== Mul1u ==
 +
 +
Unsigned multiply.
  
 
=== mul1u Src1, Src2 ===
 
=== mul1u Src1, Src2 ===
Line 174: Line 187:
  
 
== Mulel ==
 
== Mulel ==
 +
 +
Unload multiply result low.
 +
 
=== mulel Dest ===
 
=== mulel Dest ===
−
Dest = ProdLo
+
Dest = Dest <- ProdLo
  
 
Moves the value of the internal ProdLo register into the Dest register.
 
Moves the value of the internal ProdLo register into the Dest register.
Line 183: Line 199:
  
 
== Muleh ==
 
== Muleh ==
 +
 +
Unload multiply result high.
  
 
=== muleh Dest ===
 
=== muleh Dest ===
−
Dest = ProdHi
+
Dest = Dest <- ProdHi
  
 
Moves the value of the internal ProdHi register into the Dest register.
 
Moves the value of the internal ProdHi register into the Dest register.
Line 202: Line 220:
  
 
== Div1 ==
 
== Div1 ==
 +
 +
First stage of division.
  
 
=== div1 Src1, Src2 ===
 
=== div1 Src1, Src2 ===
Line 219: Line 239:
  
 
== Div2 ==
 
== Div2 ==
 +
 +
Second and later stages of division.
  
 
=== div2 Dest, Src1, Src2 ===
 
=== div2 Dest, Src1, Src2 ===
 
Quotient * Divisor + Remainder = original Remainder with bits shifted in from Src1
 
Quotient * Divisor + Remainder = original Remainder with bits shifted in from Src1
  
−
Dest = Src2 - number of bits shifted in above
+
Dest = Dest <- Src2 - number of bits shifted in above
  
 
Performs subsequent steps of division following a div1 instruction. The contents of the register Src1 is the low portion of the dividend. The contents of the register Src2 denote the number of bits in Src1 that have not yet been used before this step in the division. Dest is set to the number of bits in Src1 that have not been used after this step. The internal registers Quotient, Divisor, and Remainder are updated by this instruction.
 
Performs subsequent steps of division following a div1 instruction. The contents of the register Src1 is the low portion of the dividend. The contents of the register Src2 denote the number of bits in Src1 that have not yet been used before this step in the division. Dest is set to the number of bits in Src1 that have not been used after this step. The internal registers Quotient, Divisor, and Remainder are updated by this instruction.
Line 232: Line 254:
 
Quotient * Divisor + Remainder = original Remainder with bits shifted in from Src1
 
Quotient * Divisor + Remainder = original Remainder with bits shifted in from Src1
  
−
Dest = Imm - number of bits shifted in above
+
Dest = Dest <- Imm - number of bits shifted in above
  
 
Performs subsequent steps of division following a div1 instruction. The contents of the register Src1 is the low portion of the dividend. The immediate Imm denotes the number of bits in Src1 that have not yet been used before this step in the division. Dest is set to the number of bits in Src1 that have not been used after this step. The internal registers Quotient, Divisor, and Remainder are updated by this instruction.
 
Performs subsequent steps of division following a div1 instruction. The contents of the register Src1 is the low portion of the dividend. The immediate Imm denotes the number of bits in Src1 that have not yet been used before this step in the division. Dest is set to the number of bits in Src1 that have not been used after this step. The internal registers Quotient, Divisor, and Remainder are updated by this instruction.
Line 248: Line 270:
  
 
== Divq ==
 
== Divq ==
 +
 +
Unload division quotient.
 +
 
=== divq Dest ===
 
=== divq Dest ===
−
Dest = Quotient
+
Dest = Dest <- Quotient
  
 
Moves the value of the internal Quotient register into the Dest register.
 
Moves the value of the internal Quotient register into the Dest register.
Line 257: Line 282:
  
 
== Divr ==
 
== Divr ==
 +
 +
Unload division remainder.
 +
 
=== divr Dest ===
 
=== divr Dest ===
−
Dest = Remainder
+
Dest = Dest <- Remainder
  
 
Moves the value of the internal Remainder register into the Dest register.
 
Moves the value of the internal Remainder register into the Dest register.
Line 266: Line 294:
  
 
== Or ==
 
== Or ==
 +
 +
Logical or.
 +
 
=== or Dest, Src1, Src2 ===
 
=== or Dest, Src1, Src2 ===
−
Dest = Src1 | Src2
+
Dest = Dest <- Src1 | Src2
  
 
Computes the bitwise or of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
 
Computes the bitwise or of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
  
 
=== ori Dest, Src1, Imm ===
 
=== ori Dest, Src1, Imm ===
−
Dest = Src1 | Imm
+
Dest = Dest <- Src1 | Imm
  
 
Computes the bitwise or of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
 
Computes the bitwise or of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
Line 302: Line 333:
  
 
== And ==
 
== And ==
 +
 +
Logical And
 +
 
=== and Dest, Src1, Src2 ===
 
=== and Dest, Src1, Src2 ===
−
Dest = Src1 & Src2
+
Dest = Dest <- Src1 & Src2
  
 
Computes the bitwise and of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
 
Computes the bitwise and of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
  
 
=== andi Dest, Src1, Imm ===
 
=== andi Dest, Src1, Imm ===
−
Dest = Src1 & Imm
+
Dest = Dest <- Src1 & Imm
  
 
Computes the bitwise and of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
 
Computes the bitwise and of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
Line 338: Line 372:
  
 
== Xor ==
 
== Xor ==
 +
 +
Logical exclusive or.
 +
 
=== xor Dest, Src1, Src2 ===
 
=== xor Dest, Src1, Src2 ===
−
Dest = Src1 | Src2
+
Dest = Dest <- Src1 | Src2
  
 
Computes the bitwise xor of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
 
Computes the bitwise xor of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
  
 
=== xori Dest, Src1, Imm ===
 
=== xori Dest, Src1, Imm ===
−
Dest = Src1 | Imm
+
Dest = Dest <- Src1 | Imm
  
 
Computes the bitwise xor of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
 
Computes the bitwise xor of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
Line 374: Line 411:
  
 
== Sll ==
 
== Sll ==
 +
 +
Logical left shift.
 +
 
=== sll Dest, Src1, Src2 ===
 
=== sll Dest, Src1, Src2 ===
−
Dest = Src1 << Src2
+
Dest = Dest <- Src1 << Src2
  
 
Shifts the contents of the Src1 register to the left by the value in the Src2 register and writes the result into the Dest register. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.  
 
Shifts the contents of the Src1 register to the left by the value in the Src2 register and writes the result into the Dest register. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.  
  
 
=== slli Dest, Src1, Imm ===
 
=== slli Dest, Src1, Imm ===
−
Dest = Src1 << Imm
+
Dest = Dest <- Src1 << Imm
  
 
Shifts the contents of the Src1 register to the left by the value in the immediate Imm and writes the result into the Dest register. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
 
Shifts the contents of the Src1 register to the left by the value in the immediate Imm and writes the result into the Dest register. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
Line 397: Line 437:
  
 
== Srl ==
 
== Srl ==
 +
 +
Logical right shift.
 +
 
=== srl Dest, Src1, Src2 ===
 
=== srl Dest, Src1, Src2 ===
−
Dest = Src1 >>(logical) Src2
+
Dest = Dest <- Src1 >>(logical) Src2
  
 
Shifts the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. Bits which are shifted in sign extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.  
 
Shifts the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. Bits which are shifted in sign extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.  
  
 
=== srli Dest, Src1, Imm ===
 
=== srli Dest, Src1, Imm ===
−
Dest = Src1 >>(logical) Imm
+
Dest = Dest <- Src1 >>(logical) Imm
  
 
Shifts the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. Bits which are shifted in sign extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.  
 
Shifts the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. Bits which are shifted in sign extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.  
Line 420: Line 463:
  
 
== Sra ==
 
== Sra ==
 +
 +
Arithmetic right shift.
 +
 
=== sra Dest, Src1, Src2 ===
 
=== sra Dest, Src1, Src2 ===
−
Dest = Src1 >>(arithmetic) Src2
+
Dest = Dest <- Src1 >>(arithmetic) Src2
  
 
Shifts the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. Bits which are shifted in zero extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.  
 
Shifts the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. Bits which are shifted in zero extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.  
  
 
=== srai Dest, Src1, Imm ===
 
=== srai Dest, Src1, Imm ===
−
Dest = Src1 >>(arithmetic) Imm
+
Dest = Dest <- Src1 >>(arithmetic) Imm
  
 
Shifts the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. Bits which are shifted in zero extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.  
 
Shifts the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. Bits which are shifted in zero extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.  
Line 443: Line 489:
  
 
== Ror ==
 
== Ror ==
 +
 +
Rotate right.
 +
 
=== ror Dest, Src1, Src2 ===
 
=== ror Dest, Src1, Src2 ===
 
Rotates the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
 
Rotates the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Line 462: Line 511:
  
 
== Rcr ==
 
== Rcr ==
 +
 +
Rotate right through carry.
 +
 
=== rcr Dest, Src1, Src2 ===
 
=== rcr Dest, Src1, Src2 ===
 
Rotates the contents of the Src1 register through the carry flag and to the right by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
 
Rotates the contents of the Src1 register through the carry flag and to the right by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Line 481: Line 533:
  
 
== Rol ==
 
== Rol ==
 +
 +
Rotate left.
 +
 
=== rol Dest, Src1, Src2 ===
 
=== rol Dest, Src1, Src2 ===
 
Rotates the contents of the Src1 register to the left by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
 
Rotates the contents of the Src1 register to the left by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Line 500: Line 555:
  
 
== Rcl ==
 
== Rcl ==
 +
 +
Rotate left through carry.
 +
 
=== rcl Dest, Src1, Src2 ===
 
=== rcl Dest, Src1, Src2 ===
 
Rotates the contents of the Src1 register through the carry flag and to the left by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
 
Rotates the contents of the Src1 register through the carry flag and to the left by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Line 519: Line 577:
  
 
== Mov ==
 
== Mov ==
 +
 +
Move.
 +
 
=== mov Dest, Src1, Src2 ===
 
=== mov Dest, Src1, Src2 ===
−
Dest = Src2
+
Dest = Src1 <- Src2
  
−
Move the contents of the Src2 register into the Dest register.
+
Merge the contents of the Src2 register into the contents of Src1 and put the result into the Dest register.
  
 
=== movi Dest, Src1, Imm ===
 
=== movi Dest, Src1, Imm ===
−
Dest = Imm
+
Dest = Src1 <- Imm
  
−
Move the contents of the immediate Imm into the Dest register.
+
Merge the contents of the immediate Imm into the contents of Src1 and put the results into the Dest register.
  
 
=== Flags ===
 
=== Flags ===
Line 533: Line 594:
  
 
== Sext ==
 
== Sext ==
 +
 +
Sign extend.
 +
 
=== sext Dest, Src1, Imm ===
 
=== sext Dest, Src1, Imm ===
−
Dest = sign_extend(Src1, Imm)
+
Dest = Dest <- sign_extend(Src1, Imm)
  
 
Sign extend the value in the Src1 register starting at the bit position in the immediate Imm, and put the result in the Dest register.
 
Sign extend the value in the Src1 register starting at the bit position in the immediate Imm, and put the result in the Dest register.
Line 542: Line 606:
  
 
== Zext ==
 
== Zext ==
 +
 +
Zero extend.
 +
 
=== zext Dest, Src1, Imm ===
 
=== zext Dest, Src1, Imm ===
−
Dest = zero_extend(Src1, Imm)
+
Dest = Dest <- zero_extend(Src1, Imm)
  
 
Zero extend the value in the Src1 register starting at the bit position in the immediate Imm, and put the result in the Dest register.
 
Zero extend the value in the Src1 register starting at the bit position in the immediate Imm, and put the result in the Dest register.
Line 551: Line 618:
  
 
== Ruflag ==
 
== Ruflag ==
 +
 +
Read user flag.
 +
 
=== ruflag Dest, Imm ===
 
=== ruflag Dest, Imm ===
 
Reads the user level flag stored in the bit position specified by the immediate Imm and stores it in the register Dest.
 
Reads the user level flag stored in the bit position specified by the immediate Imm and stores it in the register Dest.
Line 595: Line 665:
  
 
== Ruflags ==
 
== Ruflags ==
 +
 +
Read all user flags.
 +
 
=== ruflags Dest ===
 
=== ruflags Dest ===
 
Dest = user flags
 
Dest = user flags
Line 604: Line 677:
  
 
== Wruflags ==
 
== Wruflags ==
 +
 +
Write all user flags.
 +
 
=== wruflags Src1, Src2 ===
 
=== wruflags Src1, Src2 ===
 
user flags = Src1 ^ Src2
 
user flags = Src1 ^ Src2
Line 618: Line 694:
  
 
== Br ==
 
== Br ==
 +
 +
Microcode branch.
 +
 
=== br Src1, Src2 ===
 
=== br Src1, Src2 ===
 
micropc = Src1 + Src2
 
micropc = Src1 + Src2
  
−
Set the micropc to the sum of the Src1 and Src2 registers. This is a microcode branch.
+
Set the micropc to the sum of the Src1 and Src2 registers.
  
 
=== bri Src1, Imm ===
 
=== bri Src1, Imm ===
 
micropc = Src1 + Imm
 
micropc = Src1 + Imm
  
−
Set the micropc to the sum of the Src1 register and immediate Imm. This is a microcode branch.
+
Set the micropc to the sum of the Src1 register and immediate Imm.
  
 
=== Flags ===
 
=== Flags ===
Line 632: Line 711:
  
 
== Rdip ==
 
== Rdip ==
 +
 +
Read the instruction pointer.
 +
 
=== rdip Dest ===
 
=== rdip Dest ===
 
Dest = rIP
 
Dest = rIP
Line 641: Line 723:
  
 
== Wrip ==
 
== Wrip ==
 +
 +
Write the instruction pointer.
 +
 
=== wrip Src1, Src2 ===
 
=== wrip Src1, Src2 ===
 
rIP = Src1 + Src2
 
rIP = Src1 + Src2
Line 653: Line 738:
 
=== Flags ===
 
=== Flags ===
 
This microop does not set any flags. It is optionally predicated.
 
This microop does not set any flags. It is optionally predicated.
 +
 +
== Chks ==
 +
Check selector.
 +
 +
Not yet implemented.
  
 
= Load/Store Ops =
 
= Load/Store Ops =
  
 
= Load immediate Op =
 
= Load immediate Op =
 +
 +
= Floating Point Ops =

Revision as of 18:00, 27 September 2007

Contents

Register Ops

Add

Addition.

add Dest, Src1, Src2

Dest = Dest <- Src1 + Src2

Adds the contents of the Src1 and Src2 registers and puts the result in the Dest register.

addi Dest, Src1, Imm

Dest = Dest <- Src1 + Imm

Adds the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF The carry out of the most significant bit.
ZF and EZF Whether the result was zero.
PF The parity of the result.
AF The carry from the 4th to 5th bit positions.
SF The sign of the result.
OF Whether there was an overflow.

Adc

Add with carry.

adc Dest, Src1, Src2

Dest = Dest <- Src1 + Src2 + CF

Adds the contents of the Src1 and Src2 registers and the carry flag and puts the result in the Dest register.

adci Dest, Src1, Imm

Dest = Dest <- Src1 + Imm + CF

Adds the contents of the Src1 register, the immediate Imm, and the carry flag and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF The carry out of the most significant bit.
ZF and EZF Whether the result was zero.
PF The parity of the result.
AF The carry from the 4th to 5th bit positions.
SF The sign of the result.
OF Whether there was an overflow.

Sub

Subtraction.

sub Dest, Src1, Src2

Dest = Dest <- Src1 - Src2

Subtracts the contents of the Src2 register from the Src1 register and puts the result in the Dest register.

subi Dest, Src1, Imm

Dest = Dest <- Src1 - Imm

Subtracts the contents of the immediate Imm from the Src1 register and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF The barrow into of the most significant bit.
ZF and EZF Whether the result was zero.
PF The parity of the result.
AF The barrow from the 5th to 4th bit positions.
SF The sign of the result.
OF Whether there was an overflow.

Sbb

Subtract with barrow.

sbb Dest, Src1, Src2

Dest = Dest <- Src1 - Src2 - CF

Subtracts the contents of the Src2 register and the carry flag from the Src1 register and puts the result in the Dest register.

sbbi Dest, Src1, Imm

Dest = Dest <- Src1 - Imm - CF

Subtracts the immediate Imm and the carry flag from the Src1 register and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF The barrow into of the most significant bit.
ZF and EZF Whether the result was zero.
PF The parity of the result.
AF The barrow from the 5th to 4th bit positions.
SF The sign of the result.
OF Whether there was an overflow.

Mul1s

Signed multiply.

mul1s Src1, Src2

ProdHi:ProdLo = Src1 * Src2

Multiplies the unsigned contents of the Src1 and Src2 registers and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.

mul1si Src1, Imm

ProdHi:ProdLo = Src1 * Imm

Multiplies the unsigned contents of the Src1 register and the immediate Imm and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.

Flags

This microop does not set any flags.

Mul1u

Unsigned multiply.

mul1u Src1, Src2

ProdHi:ProdLo = Src1 * Src2

Multiplies the unsigned contents of the Src1 and Src2 registers and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.

mul1ui Src1, Imm

ProdHi:ProdLo = Src1 * Imm

Multiplies the unsigned contents of the Src1 register and the immediate Imm and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.

Flags

This microop does not set any flags.

Mulel

Unload multiply result low.

mulel Dest

Dest = Dest <- ProdLo

Moves the value of the internal ProdLo register into the Dest register.

Flags

This microop does not set any flags.

Muleh

Unload multiply result high.

muleh Dest

Dest = Dest <- ProdHi

Moves the value of the internal ProdHi register into the Dest register.

Flags

This microop optionally sets the CF, ECF, and OF flags.

CF and ECF Whether ProdHi is non-zero
OF Whether ProdHi is non-zero.

Div1

First stage of division.

div1 Src1, Src2

Quotient * Src2 + Remainder = Src1 Divisor = Src2

Begins a division operation where the contents of SrcReg1 is the high part of the dividend and the contents of SrcReg2 is the divisor. The remainder from this partial division is put in the internal register Remainder. The quotient is put in the internal register Quotient. The divisor is put in the internal register Divisor.

div1i Src1, Imm:

Quotient * Imm + Remainder = Src1 Divisor = Imm

Begins a division operation where the contents of SrcReg1 is the high part of the dividend and the immediate Imm is the divisor. The remainder from this partial division is put in the internal register Remainder. The quotient is put in the internal register Quotient. The divisor is put in the internal register Divisor.

Flags

This microop does not set any flags.

Div2

Second and later stages of division.

div2 Dest, Src1, Src2

Quotient * Divisor + Remainder = original Remainder with bits shifted in from Src1

Dest = Dest <- Src2 - number of bits shifted in above

Performs subsequent steps of division following a div1 instruction. The contents of the register Src1 is the low portion of the dividend. The contents of the register Src2 denote the number of bits in Src1 that have not yet been used before this step in the division. Dest is set to the number of bits in Src1 that have not been used after this step. The internal registers Quotient, Divisor, and Remainder are updated by this instruction.

If there are no remaining bits in Src1, this instruction does nothing except optionally compute flags.

div2i Dest, Src1, Imm

Quotient * Divisor + Remainder = original Remainder with bits shifted in from Src1

Dest = Dest <- Imm - number of bits shifted in above

Performs subsequent steps of division following a div1 instruction. The contents of the register Src1 is the low portion of the dividend. The immediate Imm denotes the number of bits in Src1 that have not yet been used before this step in the division. Dest is set to the number of bits in Src1 that have not been used after this step. The internal registers Quotient, Divisor, and Remainder are updated by this instruction.

If there are no remaining bits in Src1, this instruction does nothing except optionally compute flags.

Flags

This microop optionally sets the EZF flag.

EZF Whether there are any remaining bits in Src1 after this step.

Divq

Unload division quotient.

divq Dest

Dest = Dest <- Quotient

Moves the value of the internal Quotient register into the Dest register.

Flags

This microop does not set any flags.

Divr

Unload division remainder.

divr Dest

Dest = Dest <- Remainder

Moves the value of the internal Remainder register into the Dest register.

Flags

This microop does not set any flags.

Or

Logical or.

or Dest, Src1, Src2

Dest = Dest <- Src1 | Src2

Computes the bitwise or of the contents of the Src1 and Src2 registers and puts the result in the Dest register.

ori Dest, Src1, Imm

Dest = Dest <- Src1 | Imm

Computes the bitwise or of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags. There is nothing that prevents computing a value for the AF flag, but it's value will be meaningless.

CF and ECF Cleared
ZF and EZF Whether the result was zero.
PF The parity of the result.
AF Undefined
SF The sign of the result.
OF Cleared

And

Logical And

and Dest, Src1, Src2

Dest = Dest <- Src1 & Src2

Computes the bitwise and of the contents of the Src1 and Src2 registers and puts the result in the Dest register.

andi Dest, Src1, Imm

Dest = Dest <- Src1 & Imm

Computes the bitwise and of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags. There is nothing that prevents computing a value for the AF flag, but it's value will be meaningless.

CF and ECF Cleared
ZF and EZF Whether the result was zero.
PF The parity of the result.
AF Undefined
SF The sign of the result.
OF Cleared

Xor

Logical exclusive or.

xor Dest, Src1, Src2

Dest = Dest <- Src1 | Src2

Computes the bitwise xor of the contents of the Src1 and Src2 registers and puts the result in the Dest register.

xori Dest, Src1, Imm

Dest = Dest <- Src1 | Imm

Computes the bitwise xor of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags. There is nothing that prevents computing a value for the AF flag, but it's value will be meaningless.

CF and ECF Cleared
ZF and EZF Whether the result was zero.
PF The parity of the result.
AF Undefined
SF The sign of the result.
OF Cleared

Sll

Logical left shift.

sll Dest, Src1, Src2

Dest = Dest <- Src1 << Src2

Shifts the contents of the Src1 register to the left by the value in the Src2 register and writes the result into the Dest register. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.

slli Dest, Src1, Imm

Dest = Dest <- Src1 << Imm

Shifts the contents of the Src1 register to the left by the value in the immediate Imm and writes the result into the Dest register. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.

Flags

This microop optionally sets the CF, ECF, and OF flags. If the shift amount is zero, no flags are modified.

CF and ECF The last bit shifted out of the result.
OF The exclusive or of the what this instruction would set the CF flag to (if requested) and the most significant bit of the result

Srl

Logical right shift.

srl Dest, Src1, Src2

Dest = Dest <- Src1 >>(logical) Src2

Shifts the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. Bits which are shifted in sign extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.

srli Dest, Src1, Imm

Dest = Dest <- Src1 >>(logical) Imm

Shifts the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. Bits which are shifted in sign extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.

Flags

This microop optionally sets the CF, ECF, and OF flags. If the shift amount is zero, no flags are modified.

CF and ECF The last bit shifted out of the result.
OF The most significant bit of the original value to shift

Sra

Arithmetic right shift.

sra Dest, Src1, Src2

Dest = Dest <- Src1 >>(arithmetic) Src2

Shifts the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. Bits which are shifted in zero extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.

srai Dest, Src1, Imm

Dest = Dest <- Src1 >>(arithmetic) Imm

Shifts the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. Bits which are shifted in zero extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.

Flags

This microop optionally sets the CF, ECF, and OF flags. If the shift amount is zero, no flags are modified.

CF and ECF The last bit shifted out of the result.
OF Cleared

Ror

Rotate right.

ror Dest, Src1, Src2

Rotates the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.

rori Dest, Src1, Imm

Rotates the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.

Flags

This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.

CF and ECF The most significant bit of the result.
OF The exclusive or of the two most significant bits of the original value.

Rcr

Rotate right through carry.

rcr Dest, Src1, Src2

Rotates the contents of the Src1 register through the carry flag and to the right by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.

rcri Dest, Src1, Imm

Rotates the contents of the Src1 register through the carry flag and to the right by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.

Flags

This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.

CF and ECF The last bit shifted out of the result.
OF The exclusive or of the CF flag before the rotate and the most significant bit of the original value.

Rol

Rotate left.

rol Dest, Src1, Src2

Rotates the contents of the Src1 register to the left by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.

roli Dest, Src1, Imm

Rotates the contents of the Src1 register to the left by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.

Flags

This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.

CF and ECF The least significant bit of the result.
OF The exclusive or of the most and least significant bits of the result.

Rcl

Rotate left through carry.

rcl Dest, Src1, Src2

Rotates the contents of the Src1 register through the carry flag and to the left by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.

rcli Dest, Src1, Imm

Rotates the contents of the Src1 register through the carry flag and to the left by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.

Flags

This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.

CF and ECF The last bit rotated out of the result.
OF The exclusive or of CF before the rotate and most significant bit of the result.

Mov

Move.

mov Dest, Src1, Src2

Dest = Src1 <- Src2

Merge the contents of the Src2 register into the contents of Src1 and put the result into the Dest register.

movi Dest, Src1, Imm

Dest = Src1 <- Imm

Merge the contents of the immediate Imm into the contents of Src1 and put the results into the Dest register.

Flags

This microop does not set any flags. It is optionally predicated.

Sext

Sign extend.

sext Dest, Src1, Imm

Dest = Dest <- sign_extend(Src1, Imm)

Sign extend the value in the Src1 register starting at the bit position in the immediate Imm, and put the result in the Dest register.

Flags

This microop does not set any flags.

Zext

Zero extend.

zext Dest, Src1, Imm

Dest = Dest <- zero_extend(Src1, Imm)

Zero extend the value in the Src1 register starting at the bit position in the immediate Imm, and put the result in the Dest register.

Flags

This microop does not set any flags.

Ruflag

Read user flag.

ruflag Dest, Imm

Reads the user level flag stored in the bit position specified by the immediate Imm and stores it in the register Dest.

The mapping between values of Imm and user level flags is show in the following table.

0 CF (carry flag)
2 PF (parity flag)
3 ECF (emulation carry flag)
4 AF (auxiliary carry flag)
5 EZF (emulation zero flag)
6 ZF (zero flag)
7 SF (sign flag)
10 DF (direction flag)
11 OF (overflow flag)

Flags

The EZF flag is always set. In the future this may become optional.

EZF Set if the value of the flag read was zero.

Ruflags

Read all user flags.

ruflags Dest

Dest = user flags

Store the user level flags into the Dest register.

Flags

This microop does not set any flags.

Wruflags

Write all user flags.

wruflags Src1, Src2

user flags = Src1 ^ Src2

Set the user level flags to the exclusive or of the Src1 and Src2 registers.

wruflagsi Src1, Imm

user flags = Src1 ^ Imm

Set the user level flags to the exclusive or of the Src1 register and the immediate Imm.

Flags

See above.

Br

Microcode branch.

br Src1, Src2

micropc = Src1 + Src2

Set the micropc to the sum of the Src1 and Src2 registers.

bri Src1, Imm

micropc = Src1 + Imm

Set the micropc to the sum of the Src1 register and immediate Imm.

Flags

This microop does not set any flags. It is optionally predicated.

Rdip

Read the instruction pointer.

rdip Dest

Dest = rIP

Set the Dest register to the current value of rIP.

Flags

This microop does not set any flags.

Wrip

Write the instruction pointer.

wrip Src1, Src2

rIP = Src1 + Src2

Set the rIP to the sum of the Src1 and Src2 registers. This causes a macroop branch at the end of the current macroop.

wripi Src1, Imm

micropc = Src1 + Imm

Set the rIP to the sum of the Src1 register and immediate Imm. This causes a macroop branch at the end of the current macroop.

Flags

This microop does not set any flags. It is optionally predicated.

Chks

Check selector.

Not yet implemented.

Load/Store Ops

Load immediate Op

Floating Point Ops

Retrieved from "http://daystrom.m5sim.org/wiki/index.php?title=X86_microop_ISA&oldid=2214"