Difference between revisions of "ARM Implementation"
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The ARM Architecture models within gem5 support an ARMv7-a profile of the ARM® architecture with multi-processor extensions. Specifically, this include support for [http://www.arm.com/products/processors/technologies/instruction-set-architectures.php Thumb®], Thumb-2, VFPv3 (32 double register variant) and [http://www.arm.com/products/processors/technologies/neon.php NEON™]. Optional features of the architecture that are not currently supported are [http://www.arm.com/products/processors/technologies/trustzone.php TrustZone®], ThumbEE, [http://www.arm.com/products/processors/technologies/jazelle.php Jazelle®], and [http://www.arm.com/products/processors/technologies/virtualization-extensions.php Virtualization and Large Physical Address Extensions (LPAE)]. | The ARM Architecture models within gem5 support an ARMv7-a profile of the ARM® architecture with multi-processor extensions. Specifically, this include support for [http://www.arm.com/products/processors/technologies/instruction-set-architectures.php Thumb®], Thumb-2, VFPv3 (32 double register variant) and [http://www.arm.com/products/processors/technologies/neon.php NEON™]. Optional features of the architecture that are not currently supported are [http://www.arm.com/products/processors/technologies/trustzone.php TrustZone®], ThumbEE, [http://www.arm.com/products/processors/technologies/jazelle.php Jazelle®], and [http://www.arm.com/products/processors/technologies/virtualization-extensions.php Virtualization and Large Physical Address Extensions (LPAE)]. | ||
| − | === | + | ===Conditional Execution Support=== |
| + | Many instructions within the ARM architecture are predicated. To handle the predication within the gem5 framework and not have to generate N varieties of each instruction for every condition code, the instructions constructors determine which, if any, conditional execution flags are set and then conditionally read the condition codes or a "zero register" which is always available and doesn't insert any dependencies in the dynamic execution of instructions. | ||
| + | |||
===Special PC management=== | ===Special PC management=== | ||
| − | + | The PCState object used for ARM® encodes additional execution state information so facilitate the use of the generic gem5 CPU components. In addition to the standard program counter, the Thumb® vs. ARM® instruction state is included as well as the ITSTATE (predication within Thumb® instructions). | |
===Boot loader=== | ===Boot loader=== | ||
A simple bootloader for ARM is in the source tree under <code>system/arm/simple_bootloader</code>. It is only needed for MP linux booting, but can be used for UP linux and probably shouldn't cause any issues with a bare metal. The initial conditions of the bootloader running are the same as those ffor Linux, <code> r0 = 0; r1 = machine number; r2 = atags ptr;</code> and some special registers for the boot loader to use <code>r3 = start address of kernel; r4 = address of GIC; r5 = adderss of flags register</code>. The bootloader works by reading the MPIDR register to determine the CPU number. CPU0 jumps immediately to the kernel while CPUn enables their interrupt interface and and wait for an interrupt. When CPU0 generates an IPI, CPUn reads the flags register until it is non-zero and then jumps to that address. | A simple bootloader for ARM is in the source tree under <code>system/arm/simple_bootloader</code>. It is only needed for MP linux booting, but can be used for UP linux and probably shouldn't cause any issues with a bare metal. The initial conditions of the bootloader running are the same as those ffor Linux, <code> r0 = 0; r1 = machine number; r2 = atags ptr;</code> and some special registers for the boot loader to use <code>r3 = start address of kernel; r4 = address of GIC; r5 = adderss of flags register</code>. The bootloader works by reading the MPIDR register to determine the CPU number. CPU0 jumps immediately to the kernel while CPUn enables their interrupt interface and and wait for an interrupt. When CPU0 generates an IPI, CPUn reads the flags register until it is non-zero and then jumps to that address. | ||
Revision as of 11:13, 10 May 2011
Contents
Supported features and modes
The ARM Architecture models within gem5 support an ARMv7-a profile of the ARM® architecture with multi-processor extensions. Specifically, this include support for Thumb®, Thumb-2, VFPv3 (32 double register variant) and NEON™. Optional features of the architecture that are not currently supported are TrustZone®, ThumbEE, Jazelle®, and Virtualization and Large Physical Address Extensions (LPAE).
Conditional Execution Support
Many instructions within the ARM architecture are predicated. To handle the predication within the gem5 framework and not have to generate N varieties of each instruction for every condition code, the instructions constructors determine which, if any, conditional execution flags are set and then conditionally read the condition codes or a "zero register" which is always available and doesn't insert any dependencies in the dynamic execution of instructions.
Special PC management
The PCState object used for ARM® encodes additional execution state information so facilitate the use of the generic gem5 CPU components. In addition to the standard program counter, the Thumb® vs. ARM® instruction state is included as well as the ITSTATE (predication within Thumb® instructions).
Boot loader
A simple bootloader for ARM is in the source tree under system/arm/simple_bootloader. It is only needed for MP linux booting, but can be used for UP linux and probably shouldn't cause any issues with a bare metal. The initial conditions of the bootloader running are the same as those ffor Linux, r0 = 0; r1 = machine number; r2 = atags ptr; and some special registers for the boot loader to use r3 = start address of kernel; r4 = address of GIC; r5 = adderss of flags register. The bootloader works by reading the MPIDR register to determine the CPU number. CPU0 jumps immediately to the kernel while CPUn enables their interrupt interface and and wait for an interrupt. When CPU0 generates an IPI, CPUn reads the flags register until it is non-zero and then jumps to that address.
