Difference between revisions of "InOrder"

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This page provides a general overview of the InOrderCPU model, its pipeline stages, and its resources.
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== Overview ==
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The InOrder CPU model was designed to provide a generic framework to simulate in-order pipelines with an arbitrary ISA and with arbitrary pipeline descriptions. The model was originally conceived by closely mirroring the O3CPU model to provide a simulation framework that would operate at the "Tick" granularity. We then abstract the individual stages in the O3 model to provide [[InOrder Pipeline Stages | generic pipeline stages]] for the InOrder CPU to leverage in creating a user-defined amount of pipeline stages. Additionally, we abstract each component that a CPU might need to access (ALU, Branch Predictor, etc.) into a "resource" that needs to be requested by each instruction according to the [[InOrder Resource-Request Model | resource-request]] model we implemented. This will potentially allow for researchers to model custom pipelines without the cost of designing the complete CPU from scratch.
  
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The relevant sources files are in src/cpu/inorder.
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For more information, please check the following documentation about the InOrder model, browse the code, and also access the gem5-users@m5sim.org (standard usage) or gem5-dev@m5sim.org (for developer)
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mailing lists:
  
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== Pipeline Stages ==
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* [[InOrder Pipeline Stages | Pipeline Stages]]
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The InOrderCPU models 5-stage and 9-stage pipelines. The 5-stage pipeline is based on the 5-stage MIPS pipeline and has the following stages:
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* [[InOrder Resource-Request Model | Resource-Request Modeling]]
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* Instruction Fetch (IF)
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* [[InOrder Instruction Schedules | Instruction Schedules & Pipeline Descriptions]]
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* Instruction Decode (ID)
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* [[InOrder Tutorial | A Day in the Life of an Instruction in the InOrderCPU model (Not Completed)]]
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* Execute (EX)
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*Other Links:
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* Memory Access (MEM)
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**Soumyaroop Roy has been kind enough to provide a [http://www.csee.usf.edu/~sroy/techres/m5_tests/"test-status-page"] of the M5-Inorder model in the work he has been doing.
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* Register Write Back (WB)
 
  
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Relevant source files:
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== Current Development ==
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* first_stage.[hh,cc]
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'''Latest versions of the InOrderCPU model can be found in the gem5-dev repository'''
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* pipeline_stage.[hh,cc]
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* [[InOrder ToDo List]]
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== Pipeline Resources ==
 
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The following pipeline resources are defined for InOrderCPU:
 
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* Fetch Unit
 
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* Instruction Cache (I-Cache)
 
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* Branch Prediction Unit (BPred Unit)
 
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* Register File Manager (RF Manager)
 
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* Address Generation Unit (AGen Unit)
 
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* Execution Unit (EXU)
 
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* Integer Multiply and Divide Unit (Int MDU)
 
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* Data Cache (D-Cache)
 
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* Graduation Unit (Grad Unit)
 
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Relevant source files:
 
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* resources/*.[hh,cc]
 
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== Resource Pool ==
 
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@TODO
 
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== Pipeline Definition ==
 
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@TODO
 
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== Instruction Schedules ==
 
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Instruction scheduling is divided into a ''front-end schedule'' (IF and ID), which is uniform for all the instructions, and a ''back-end schedule'', which varies across the different instructions.
 
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* Front-end Schedule
 
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** The front-end schedule comprises of the IF and ID stages
 
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*** IF
 
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**** NPC is updated by the Fetch unit
 
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**** Instruction fetch from the I-Cache is initiated
 
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*** ID
 
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**** Instruction fetch is completed by I-Cache
 
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**** Instruction decode is performed by the Decode unit
 
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**** Branch prediction is performed by the BPred unit
 
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**** Target PC is updated by the Fetch unit
 
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* Back-end Schedule
 
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** The back-end schedule comprises of the ID, EX, MEM, and WB stages
 
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*** ID
 
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**** For non-store instructions, the source registers, if any, are read by the RF Manager
 
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**** For load instructions, address generation is performed by the AGEN unit and data read from the D-Cache is initiated
 
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**** The rest of the instructions are executed in the execution units
 
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***** Single cycle operations are sent to the integer EXU
 
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***** Execution is initiated for the multicycle/pipelined operations
 
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*** EX
 
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**** Execution is finished for the multicycle/pipelined operations
 
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**** For load instructions, data read from the D-Cache is completed
 
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**** For store instructions, the following tasks are performed
 
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***** The source registers are read by the RF manager
 
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***** Address generation is performed by the AGen unit
 
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***** Data write into the D-Cache is initiated
 
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*** MEM
 
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**** For store instructions, data write into the D-Cache is completed
 
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*** WB
 
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**** Destination registers are written into by the RF manager
 
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**** The instruction is graduated by the Grad unit
 
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Relevant source files:
 
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* pipeline_traits.[cc,hh]
 

Latest revision as of 06:59, 19 June 2011

Overview

The InOrder CPU model was designed to provide a generic framework to simulate in-order pipelines with an arbitrary ISA and with arbitrary pipeline descriptions. The model was originally conceived by closely mirroring the O3CPU model to provide a simulation framework that would operate at the "Tick" granularity. We then abstract the individual stages in the O3 model to provide generic pipeline stages for the InOrder CPU to leverage in creating a user-defined amount of pipeline stages. Additionally, we abstract each component that a CPU might need to access (ALU, Branch Predictor, etc.) into a "resource" that needs to be requested by each instruction according to the resource-request model we implemented. This will potentially allow for researchers to model custom pipelines without the cost of designing the complete CPU from scratch.

For more information, please check the following documentation about the InOrder model, browse the code, and also access the gem5-users@m5sim.org (standard usage) or gem5-dev@m5sim.org (for developer) mailing lists:

Current Development

Latest versions of the InOrderCPU model can be found in the gem5-dev repository

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