Difference between revisions of "Status Matrix"
From gem5
(add note about x86 locked accesses not working on classic caches in timing mode) |
(a little more cleanup and compaction) |
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|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | |MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | ||
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|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | |MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | ||
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|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | |MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | ||
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|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | |MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | ||
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!rowspan="2"|SE | !rowspan="2"|SE | ||
| − | | | + | |uni |
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| style="background: orange; color: white"| | | style="background: orange; color: white"| | ||
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| style="background: red; color: white" | Note 3 | | style="background: red; color: white" | Note 3 | ||
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| − | | | + | |uni |
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| style="background: red; color: white" | Note 3 | | style="background: red; color: white" | Note 3 | ||
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!colspan="6"|Memory System | !colspan="6"|Memory System | ||
|- | |- | ||
| − | !rowspan="2"| | + | !rowspan="2"|Model |
!rowspan="2"|System | !rowspan="2"|System | ||
| − | !rowspan="2"| | + | !rowspan="2"|Count |
!rowspan="2"|Classic | !rowspan="2"|Classic | ||
!colspan="5"|Ruby | !colspan="5"|Ruby | ||
| Line 665: | Line 665: | ||
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | |MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | ||
|- | |- | ||
| − | !rowspan="4"| | + | !rowspan="4"|AtomicSimple |
!rowspan="2"|SE | !rowspan="2"|SE | ||
| − | | | + | |uni |
| style="background: yellow;" | | | style="background: yellow;" | | ||
| style="background: red; color: white" | Note 1 | | style="background: red; color: white" | Note 1 | ||
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!rowspan="2"|SE | !rowspan="2"|SE | ||
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| style="background: red; color: white" | Note 3 | | style="background: red; color: white" | Note 3 | ||
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| style="background: red; color: white" | Note 3 | | style="background: red; color: white" | Note 3 | ||
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!colspan="6"|Memory System | !colspan="6"|Memory System | ||
|- | |- | ||
| − | !rowspan="2"| | + | !rowspan="2"|Model |
!rowspan="2"|System | !rowspan="2"|System | ||
| − | !rowspan="2"| | + | !rowspan="2"|Count |
!rowspan="2"|Classic | !rowspan="2"|Classic | ||
!colspan="5"|Ruby | !colspan="5"|Ruby | ||
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|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | |MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token | ||
|- | |- | ||
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| style="background: red; color: white" | Note 3 | | style="background: red; color: white" | Note 3 | ||
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| style="background: red; color: white" | Note 3 | | style="background: red; color: white" | Note 3 | ||
Revision as of 20:03, 18 September 2011
The follow six tables describe the current state of component combinations in gem5.
Contents
Color Key
| Definitely does not work |
| Might work |
| Should work |
| Definitely works |
| Unknown |
Notes
Numbers in the squares below refer to the following notes:
- Ruby does not support atomic-mode accesses
- The MI_example protocol cannot support LL/SC semantics
- Ruby does not support probing the O3 LSQ to enforce non-weak consistency models
- ARM MP does not support booting with caches, but works otherwise. You can boot without caches then switch to running with caches using either a checkpoint/resume or on-line CPU switchover.
- Classic caches do not support x86 locked (atomic RMW) accesses. The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.
ISA Support Matrices
Alpha
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | Note 2 | |||||||
| FS | uni | |||||||
| multi | Note 2 | |||||||
| InOrder | SE | uni | ||||||
| multi | Note 2 | |||||||
| FS | uni | |||||||
| multi | Note 2 | |||||||
| O3 | SE | uni | ||||||
| multi | Note 2 | Note 3 | Note 3 | Note 3 | Note 3 | |||
| FS | uni | |||||||
| multi | Note 2 | Note 3 | Note 3 | Note 3 | Note 3 | |||
x86
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | Note 5 | |||||||
| FS | uni | |||||||
| multi | Note 5 | |||||||
| InOrder | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| O3 | SE | uni | ||||||
| multi | Note 5 | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | ||
| FS | uni | |||||||
| multi | Note 5 | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | ||
ARM
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 4 | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| TimingSimple | SE | uni | ||||||
| multi | Note 2 | |||||||
| FS | uni | |||||||
| multi | Note 4 | Note 2 | ||||||
| InOrder | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| O3 | SE | uni | ||||||
| multi | Note 2 | Note 3 | Note 3 | Note 3 | Note 3 | |||
| FS | uni | |||||||
| multi | Note 4 | Note 2 | Note 3 | Note 3 | Note 3 | Note 3 | ||
SPARC
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| InOrder | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| O3 | SE | uni | ||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
| FS | uni | |||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
PowerPC
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| InOrder | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| O3 | SE | uni | ||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
| FS | uni | |||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
MIPS
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| InOrder | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| O3 | SE | uni | ||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
| FS | uni | |||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
