Difference between revisions of "TraceCPU"

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(Created page with " == Headline text == Introduction The goal of this project is to achieve performance estimation in a fast and accurate way by capturing and replaying dependency and timing an...")
 
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== Headline text ==
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== Overview ==
Introduction
 
  
The goal of this project is to achieve performance estimation in a fast and accurate way by capturing and replaying dependency and timing annotated traces instead of using a detailed but slow CPU model. The focus is on data memory accesses which are presumably the bulk traffic to conduct performance estimation studies of different interconnect and memories.
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The Trace CPU model plays back ''elastic traces'', which are dependency and timing annotated traces generated by the Elastic Trace Probe attached to the O3 CPU model. The focus of the Trace CPU model is to achieve memory-system (cache-hierarchy, interconnects and main memory) performance exploration in a fast and reasonably accurate way instead of using the detailed but slow O3 CPU model.
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The traces have been developed for single-threaded benchmarks simulating in both SE and FS mode. They have been correlated for 15 memory-sensitive SPEC 2006 benchmarks and a handful of HPC proxy apps by interfacing the Trace CPU with classic memory system and varying cache design parameters and DRAM memory type. In general, elastic traces can be ported to other simulation environments.
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[[File:Etrace_methodology.jpg]|800px]

Revision as of 09:55, 10 December 2015

Overview

The Trace CPU model plays back elastic traces, which are dependency and timing annotated traces generated by the Elastic Trace Probe attached to the O3 CPU model. The focus of the Trace CPU model is to achieve memory-system (cache-hierarchy, interconnects and main memory) performance exploration in a fast and reasonably accurate way instead of using the detailed but slow O3 CPU model.

The traces have been developed for single-threaded benchmarks simulating in both SE and FS mode. They have been correlated for 15 memory-sensitive SPEC 2006 benchmarks and a handful of HPC proxy apps by interfacing the Trace CPU with classic memory system and varying cache design parameters and DRAM memory type. In general, elastic traces can be ported to other simulation environments.

[[File:Etrace_methodology.jpg]|800px]