Difference between revisions of "Status Matrix"

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 +
The follow six tables describe the current state of component combinations in gem5.
 +
 +
== Color Key ==
 +
{| border="1" class="wikitable"
 +
| style="background: red; color: white" | Definitely does not work
 +
|-
 +
| style="background: orange; color: white" | Might work
 +
|-
 +
| style="background: yellow" | Should work
 +
|-
 +
| style="background: green; color: white" | Definitely works
 +
|-
 +
| style="background: purple; color: white" | Unknown
 +
|-
 +
|}
 +
 +
== Notes ==
 +
Below [[Classic Memory System | Classic]] and [[Ruby]] refers to the two memory systems that we have in gem5. [[MI_example|MI]], [[MESI Two Level | MESI]] and [[Ruby#SLICC + Coherence protocols: | MOESI]] (multiple flavors) are the coherence protocols that are supported in Ruby memory system. Then we have the CPU models: [[SimpleCPU | AtomicSimple]], [[SimpleCPU | TimingSimple]], [[InOrder]] and [[O3CPU | O3]].
 +
 +
Numbers in the squares below refer to the following notes:
 +
 +
# Ruby does not support atomic-mode accesses
 +
# The MI_example protocol cannot support LL/SC semantics
 +
# Classic caches do not support x86 locked (atomic RMW) accesses.  The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.
 +
 +
== ISA Support Matrices ==
 +
 +
'''''THIS PAGE WAS LAST UPDATED IN 2015. IT IS LIKELY OUT OF DATE. USE THIS AS A GUIDELINE.'''''
 +
 
=== Alpha ===
 
=== Alpha ===
  
−
{| border="1"
+
{| border="1" class="wikitable" align=center style="background:#B0C4DE;"
 
!colspan="3"|Processor
 
!colspan="3"|Processor
 
!colspan="6"|Memory System
 
!colspan="6"|Memory System
 
|-
 
|-
−
!rowspan="2"|Cpu Model
+
!rowspan="2"|Model
 
!rowspan="2"|System
 
!rowspan="2"|System
−
!rowspan="2"|Processor Count
+
!rowspan="2"|Count
 
!rowspan="2"|Classic
 
!rowspan="2"|Classic
 
!colspan="5"|Ruby
 
!colspan="5"|Ruby
Line 13: Line 42:
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|-
 
|-
−
!rowspan="4"|Atomic
+
!rowspan="4"|AtomicSimple
−
!rowspan="2"|SE
+
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 
|-
 
|-
 
!rowspan="4"|TimingSimple
 
!rowspan="4"|TimingSimple
 
!rowspan="2"|SE
 
!rowspan="2"|SE
−
|uniprocessor
+
|uni
 +
| style="background: green; color: white" |
 +
| style="background: green; color: white" |
 +
| style="background: green; color: white" |
 +
| style="background: green; color: white" |
 +
| style="background: green; color: white" |
 +
| style="background: green; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: green; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: green; color: white" |
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 +
| style="background: green; color: white" |
 +
| style="background: green; color: white" |
 +
| style="background: green; color: white" |
 +
| style="background: green; color: white" |
 +
| style="background: green; color: white" |
 +
| style="background: green; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: green; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: green; color: white" |
 
|-
 
|-
−
!rowspan="4"|In-Order
+
!rowspan="4"|InOrder
 
!rowspan="2"|SE
 
!rowspan="2"|SE
−
|uniprocessor
+
|uni
 +
| style="background: green; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 +
| style="background: green; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 
|-
 
|-
−
!rowspan="4"|o3
+
!rowspan="4"|O3
 
!rowspan="2"|SE
 
!rowspan="2"|SE
−
|uniprocessor
+
|uni
 +
| style="background: green; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 +
| style="background: green; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 
|-
 
|-
 
|}
 
|}
  
−
=== x86 ===
+
=== ARM ===
  
−
http://m5sim.org/wiki/index.php/x86_Status_Matrix
+
{| border="1" class="wikitable" align=center style="background:#B0C4DE;"
 +
!colspan="3"|Processor
 +
!colspan="6"|Memory System
 +
|-
 +
!rowspan="2"|Model
 +
!rowspan="2"|System
 +
!rowspan="2"|Count
 +
!rowspan="2"|Classic
 +
!colspan="5"|Ruby
 +
|-
 +
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 +
|-
 +
!rowspan="4"|AtomicSimple
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
!rowspan="4"|TimingSimple
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: green; color: white" |
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white"| Note 2
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: green; color: white" |
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white"| Note 2
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
!rowspan="4"|InOrder
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
!rowspan="4"|O3
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: green; color: white" |
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white"| Note 2
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white"| Note 2
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white"| Note 2
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
|}
  
−
=== ARM ===
+
=== x86 ===
  
−
http://m5sim.org/wiki/index.php/ARM_Status_Matrix
+
{| border="1" class="wikitable" align=center style="background:#B0C4DE;"
 +
!colspan="3"|Processor
 +
!colspan="6"|Memory System
 +
|-
 +
!rowspan="2"|Model
 +
!rowspan="2"|System
 +
!rowspan="2"|Count
 +
!rowspan="2"|Classic
 +
!colspan="5"|Ruby
 +
|-
 +
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 +
|-
 +
!rowspan="4"|AtomicSimple
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: yellow;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
|multi
 +
| style="background: yellow;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: yellow;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
|multi
 +
| style="background: yellow;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
!rowspan="4"|TimingSimple
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: yellow;" |
 +
| style="background: yellow;" |
 +
| style="background: yellow;" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow;" |
 +
|-
 +
|multi
 +
| style="background: yellow;" | Note 3
 +
| style="background: yellow;" |
 +
| style="background: yellow;" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow;" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: yellow;" | Note 3
 +
| style="background: yellow;" |
 +
| style="background: yellow;" |
 +
| style="background: green; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow;" |
 +
|-
 +
|multi
 +
| style="background: yellow;" | Note 3
 +
| style="background: yellow;" |
 +
| style="background: yellow;" |
 +
| style="background: green; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow;" |
 +
|-
 +
!rowspan="4"|InOrder
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
!rowspan="4"|O3
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: yellow;" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
|-
 +
|multi
 +
| style="background: yellow;" | Note 3
 +
| style="background: red; color: white" | Note 2
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: orange; color: white" | Note 3
 +
| style="background: red; color: white" | Note 2
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
|-
 +
|multi
 +
| style="background: orange; color: white" | Note 3
 +
| style="background: red; color: white" | Note 2
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
| style="background: yellow; color: white" |
 +
|-
 +
|}
  
 
=== SPARC ===
 
=== SPARC ===
  
−
http://m5sim.org/wiki/index.php/SPARC_Status_Matrix
+
{| border="1" class="wikitable" align=center style="background:#B0C4DE;"
 +
!colspan="3"|Processor
 +
!colspan="6"|Memory System
 +
|-
 +
!rowspan="2"|Model
 +
!rowspan="2"|System
 +
!rowspan="2"|Count
 +
!rowspan="2"|Classic
 +
!colspan="5"|Ruby
 +
|-
 +
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 +
|-
 +
!rowspan="4"|AtomicSimple
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: yellow;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
|multi
 +
| style="background: yellow;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: orange; color: white" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
|multi
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
!rowspan="4"|TimingSimple
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: yellow;" |
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
|multi
 +
| style="background: yellow;" |
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
|multi
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
!rowspan="4"|InOrder
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
!rowspan="4"|O3
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: yellow;" |
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
|multi
 +
| style="background: yellow;" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |Note 2
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|}
  
 
=== PowerPC ===
 
=== PowerPC ===
  
−
http://m5sim.org/wiki/index.php/PowerPC_Status_Matrix
+
{| border="1" class="wikitable" align=center style="background:#B0C4DE;"
 +
!colspan="3"|Processor
 +
!colspan="6"|Memory System
 +
|-
 +
!rowspan="2"|Model
 +
!rowspan="2"|System
 +
!rowspan="2"|Count
 +
!rowspan="2"|Classic
 +
!colspan="5"|Ruby
 +
|-
 +
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 +
|-
 +
!rowspan="4"|AtomicSimple
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: yellow;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
|multi
 +
| style="background: orange;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: red;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
|multi
 +
| style="background: red;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
|-
 +
!rowspan="4"|TimingSimple
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: yellow;" |
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
|-
 +
|multi
 +
| style="background: orange;" |
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: red;" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: red;" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
!rowspan="4"|InOrder
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
|-
 +
|multi
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
!rowspan="4"|O3
 +
!rowspan="2"|SE
 +
|uni
 +
| style="background: yellow;" |
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
|-
 +
|multi
 +
| style="background: orange;" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
|-
 +
!rowspan="2"|FS
 +
|uni
 +
| style="background: red;" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: red;" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|}
  
 
=== MIPS ===
 
=== MIPS ===
  
−
http://m5sim.org/wiki/index.php/MIPS_Status_Matrix
+
{| border="1" class="wikitable" align=center style="background:#B0C4DE;"
−
 
 
−
{| border="1"
 
 
!colspan="3"|Processor
 
!colspan="3"|Processor
 
!colspan="6"|Memory System
 
!colspan="6"|Memory System
 
|-
 
|-
−
!rowspan="2"|Cpu Model
+
!rowspan="2"|Model
 
!rowspan="2"|System
 
!rowspan="2"|System
−
!rowspan="2"|Processor Count
+
!rowspan="2"|Count
 
!rowspan="2"|Classic
 
!rowspan="2"|Classic
 
!colspan="5"|Ruby
 
!colspan="5"|Ruby
Line 91: Line 822:
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|-
 
|-
−
!rowspan="4"|Atomic
+
!rowspan="4"|AtomicSimple
−
!rowspan="2"|SE
+
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 +
| style="background: yellow;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: orange;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 +
| style="background: red;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: red;" |
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 +
| style="background: red; color: white" | Note 1
 
|-
 
|-
 
!rowspan="4"|TimingSimple
 
!rowspan="4"|TimingSimple
−
!rowspan="2"|SE
+
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 +
| style="background: yellow;" |
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: orange;" |
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 +
| style="background: red;" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: red;" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 
|-
 
|-
−
!rowspan="4"|In-Order
+
!rowspan="4"|InOrder
−
!rowspan="2"|SE
+
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 +
| style="background: red;" |
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: red;" |
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 
|-
 
|-
−
!rowspan="4"|o3
+
!rowspan="4"|O3
−
!rowspan="2"|SE
+
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 +
| style="background: yellow;" |
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white"|
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: orange;" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 +
| style="background: purple; color: white" |
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 +
| style="background: red;" |
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white"|
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 
|-
 
|-
−
|mulitprocessor
+
|multi
 +
| style="background: red;" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 
|-
 
|-
 
|}
 
|}

Latest revision as of 12:06, 23 February 2018

The follow six tables describe the current state of component combinations in gem5.

Color Key

Definitely does not work
Might work
Should work
Definitely works
Unknown

Notes

Below Classic and Ruby refers to the two memory systems that we have in gem5. MI, MESI and MOESI (multiple flavors) are the coherence protocols that are supported in Ruby memory system. Then we have the CPU models: AtomicSimple, TimingSimple, InOrder and O3.

Numbers in the squares below refer to the following notes:

  1. Ruby does not support atomic-mode accesses
  2. The MI_example protocol cannot support LL/SC semantics
  3. Classic caches do not support x86 locked (atomic RMW) accesses. The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.

ISA Support Matrices

THIS PAGE WAS LAST UPDATED IN 2015. IT IS LIKELY OUT OF DATE. USE THIS AS A GUIDELINE.

Alpha

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi Note 2
FS uni
multi Note 2
InOrder SE uni
multi Note 2
FS uni
multi Note 2
O3 SE uni
multi Note 2
FS uni
multi Note 2

ARM

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi Note 2
FS uni
multi Note 2
InOrder SE uni
multi
FS uni
multi
O3 SE uni
multi Note 2
FS uni Note 2
multi Note 2

x86

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi Note 3
FS uni Note 3
multi Note 3
InOrder SE uni
multi
FS uni
multi
O3 SE uni
multi Note 3 Note 2
FS uni Note 3 Note 2
multi Note 3 Note 2

SPARC

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi
FS uni
multi
InOrder SE uni
multi
FS uni
multi
O3 SE uni
multi Note 2
FS uni
multi Note 2

PowerPC

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi
FS uni
multi
InOrder SE uni
multi
FS uni
multi
O3 SE uni
multi Note 2
FS uni
multi Note 2

MIPS

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi
FS uni
multi
InOrder SE uni
multi
FS uni
multi
O3 SE uni
multi Note 2
FS uni
multi Note 2
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