Difference between revisions of "ICS2018 gem5 SVE Tutorial"
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| − | =Vector Architecture Exploration with gem5 ( | + | =Vector Architecture Exploration with gem5 (Arm)= |
==Abstract== | ==Abstract== | ||
The Arm Scalable Vector Extension (SVE) is a key enabling technology to accelerate HPC and machine learning workloads on future Arm-based processors. SVE does not set a specific vector length, which is microarchitecture-specific. This vector-length agnosticism increases design space complexity and exacerbates the importance of having flexible and accurate modeling tools. | The Arm Scalable Vector Extension (SVE) is a key enabling technology to accelerate HPC and machine learning workloads on future Arm-based processors. SVE does not set a specific vector length, which is microarchitecture-specific. This vector-length agnosticism increases design space complexity and exacerbates the importance of having flexible and accurate modeling tools. | ||
| Line 9: | Line 9: | ||
==Target Audience== | ==Target Audience== | ||
| − | The primary audience are computer architect engineers both in academia (e.g., graduate students) and in industry who want to learn about the Arm Scalable Vector | + | The primary audience are computer architect engineers both in academia (e.g., graduate students) and in industry who want to learn about the Arm Scalable Vector Extension (SVE) and the Arm tools for SVE, or are planning to use gem5 for architecture research, especially if they plan to explore Arm vector architectures. The tutorial is also expected to be useful as a high-level introduction to gem5 and how it can be used for architecture research. |
Prerequisites: working knowledge of computer systems, vector architectures, C++ and Python is recommended. | Prerequisites: working knowledge of computer systems, vector architectures, C++ and Python is recommended. | ||
| − | ==Schedule | + | ==Schedule== |
{| class="wikitable" width="75%" style="margin: 1em auto 1em auto" | {| class="wikitable" width="75%" style="margin: 1em auto 1em auto" | ||
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! width="50"|Time | ! width="50"|Time | ||
|- | |- | ||
| − | | | + | | Welcome || style="text-align:right"| 1:30pm |
|- | |- | ||
| − | | The Arm Scalable Vector Extension || style="text-align:right"| | + | | The Arm Scalable Vector Extension || style="text-align:right"| 1:40pm |
|- | |- | ||
| − | | Vector Architecture Design and Tools || style="text-align:right"| | + | | Vector Architecture Design Trade-offs and Tools || style="text-align:right"| 2:10pm |
|- | |- | ||
| − | | Introduction to gem5 || style="text-align:right"| | + | | Introduction to gem5 || style="text-align:right"| 2:45pm |
|- | |- | ||
|- style="background:lightgray" | |- style="background:lightgray" | ||
| − | | Break || style="text-align:right"| | + | | Break || style="text-align:right"| 3:00pm |
|- | |- | ||
| − | | gem5 Basics || style="text-align:right"| | + | | gem5 Basics || style="text-align:right"| 3:30pm |
|- | |- | ||
| − | | gem5 Advanced Features || style="text-align:right"| | + | | gem5 Advanced Features || style="text-align:right"| 4:05pm |
|- | |- | ||
| − | | SVE gem5 Simulation || style="text-align:right"| | + | | SVE gem5 Simulation || style="text-align:right"| 4:40pm |
|- | |- | ||
| − | | Closing || style="text-align:right"| 5 | + | | Closing || style="text-align:right"| 5:15pm |
|} | |} | ||
| + | |||
| + | ==Slides== | ||
| + | |||
| + | [https://www.rico.cat/files/ICS18-gem5-sve-tutorial.pdf Slides - Vector Architecture Exploration with gem5] | ||
==Organizers== | ==Organizers== | ||
| − | Tutorial organized by Alex Rico | + | Tutorial organized by Alex Rico, Jose Joao and Giacomo Gabrielli of Arm |
Latest revision as of 20:23, 14 June 2018
Contents
Vector Architecture Exploration with gem5 (Arm)
Abstract
The Arm Scalable Vector Extension (SVE) is a key enabling technology to accelerate HPC and machine learning workloads on future Arm-based processors. SVE does not set a specific vector length, which is microarchitecture-specific. This vector-length agnosticism increases design space complexity and exacerbates the importance of having flexible and accurate modeling tools.
gem5 is an open-source full-system microarchitectural simulator that is widely used in academia and industry. Arm is a major contributor to gem5 and has developed and upstreamed many features and models. SVE support in gem5 is being finalized to be made publicly available to enable users to simulate multi-core architectures with SVE using Arm-provided timing models.
This tutorial covers the features of SVE, the trade-offs of designing a multi-core that uses vectors, and the publicly available tools to model the performance of such vector architectures, with an emphasis on gem5 with SVE support. In addition to gem5, the tutorial will also cover other analysis tools for SVE, such as the Arm Instruction Emulator, which will be made available to the participants through docker images to provide a quick start in these environments.
Target Audience
The primary audience are computer architect engineers both in academia (e.g., graduate students) and in industry who want to learn about the Arm Scalable Vector Extension (SVE) and the Arm tools for SVE, or are planning to use gem5 for architecture research, especially if they plan to explore Arm vector architectures. The tutorial is also expected to be useful as a high-level introduction to gem5 and how it can be used for architecture research.
Prerequisites: working knowledge of computer systems, vector architectures, C++ and Python is recommended.
Schedule
| Topic | Time |
|---|---|
| Welcome | 1:30pm |
| The Arm Scalable Vector Extension | 1:40pm |
| Vector Architecture Design Trade-offs and Tools | 2:10pm |
| Introduction to gem5 | 2:45pm |
| Break | 3:00pm |
| gem5 Basics | 3:30pm |
| gem5 Advanced Features | 4:05pm |
| SVE gem5 Simulation | 4:40pm |
| Closing | 5:15pm |
Slides
Slides - Vector Architecture Exploration with gem5
Organizers
Tutorial organized by Alex Rico, Jose Joao and Giacomo Gabrielli of Arm
