Difference between revisions of "Publications"

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===2006===
 
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===2003===
 
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* ''The Impact of Resource Partitioning on SMT Processors''.  S. E. Raasch and S. K. Reinhardt.  Proc. 12th Int'l Conf. on Parallel Architectures and Compilation Techniques (PACT), pp. 15-25, Sept. 2003.  [http://www.eecs.umich.edu/~stever/pubs/pact03.pdf">pdf]
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* ''The Impact of Resource Partitioning on SMT Processors''.  S. E. Raasch and S. K. Reinhardt.  Proc. 12th Int'l Conf. on Parallel Architectures and Compilation Techniques (PACT), pp. 15-25, Sept. 2003.  [http://www.eecs.umich.edu/~stever/pubs/pact03.pdf pdf]
  
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* ''Network-Oriented Full-System Simulation using M5''.  N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt.  Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2003.  [http://www.eecs.umich.edu/~stever/pubs/caecw03.pdf">pdf]
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* ''Network-Oriented Full-System Simulation using M5''.  N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt.  Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2003.  [http://www.eecs.umich.edu/~stever/pubs/caecw03.pdf pdf]
  
 
* ''Design, Implementation and Use of the MIRV Experimental Compiler for Computer Architecture Research''.  D. A. Greene. Dissertation at the Universtiy of Michigan, 2003.  [http://www.eecs.umich.edu/~tnm/theses/daveg.pdg">pdf ]
 
* ''Design, Implementation and Use of the MIRV Experimental Compiler for Computer Architecture Research''.  D. A. Greene. Dissertation at the Universtiy of Michigan, 2003.  [http://www.eecs.umich.edu/~tnm/theses/daveg.pdg">pdf ]
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* ''A Scalable Instruction Queue Design Using Dependence Chains''.  S. E. Raasch, N. L. Binkert, and S. K. Reinhardt.  Proc. 29th Annual Int'l Symp. on Computer Architecture (ISCA), pp. 318-329, May 2002.  [http://www.eecs.umich.edu/~stever/pubs/isca02_segiq.pdf pdf] [http://www.eecs.umich.edu/~stever/pubs/isca02_segiq.ps ps] [http://www.eecs.umich1111/~stever/pubs/isca02_segiq.ps.gz ps.gz]
 
* ''A Scalable Instruction Queue Design Using Dependence Chains''.  S. E. Raasch, N. L. Binkert, and S. K. Reinhardt.  Proc. 29th Annual Int'l Symp. on Computer Architecture (ISCA), pp. 318-329, May 2002.  [http://www.eecs.umich.edu/~stever/pubs/isca02_segiq.pdf pdf] [http://www.eecs.umich.edu/~stever/pubs/isca02_segiq.ps ps] [http://www.eecs.umich1111/~stever/pubs/isca02_segiq.ps.gz ps.gz]
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</div>__NOTOC__

Revision as of 15:46, 7 June 2006

2006

  • A Simple Integrated Network Interface for High-Bandwidth Servers. N. L. Binkert, A. G. Saidi, S. K. Reinhardt. University of Michigan Technical Report CSE-TR-514-06, January 2006. pdf

2005

  • How to Fake 1000 Registers. D. W. Oehmke, N. L. Binkert, S. K. Reinhardt, and T. Mudge. Proc. 38th Ann. Int'l Symp. on Microarchitecture (MICRO), November 2005. pdf
  • Virtualizing Register Context. D. W. Oehmke. Dissertation at the University of Michigan, 2005. pdf
  • Performance Validation of Network-Intensive Workloads on a Full-System Simulator. A. G. Saidi, N. L. Binkert, L. R. Hsu, and S. K. Reinhardt. First Ann. Workshop on Iteraction between Operating System and Computer Architecture (IOSCA), October 2005. pdf
    • An extended version appears as University of Michigan Technical Report CSE-TR-511-05, July 2005. pdf
  • Performance Analysis of System Overheads in TCP/IP Workloads. N. L. Binkert, L. R. Hsu, A. G. Saidi, R. G. Dreslinski, A. L. Schultz, and S. K. Reinhardt. Proc. 14th Int'l Conf. on Parallel Architectures and Compilation Techniques (PACT), September 2005. pdf
  • Sampling and Stability in TCP/IP Workloads. L. R. Hsu, A. G. Saidi, N. L. Binkert, and S. K. Reinhardt. Proc. First Annual Workshop on Modeling, Benchmarking, and Simulation (MoBS), June 2005. pdf
  • A Unified Compressed Memory Hierarchy. E. G. Hallnor and S. K. Reinhardt. Proc. 11th Int'l Symp. on High-Performance Computer Architecture (HPCA), February 2005. pdf
  • Analyzing NIC Overheads in Network-Intensive Workloads. N. L. Binkert, L. R. Hsu, A. G. Saidi, R. G. Dreslinski, A. L. Schultz, and S. K. Reinhardt. Eighth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2005. pdf
    • An extended version appears as University of Michigan Technical Report CSE-TR-505-04, December 2004. pdf

2004

  • Emulation of realisitic network traffic patterns on an eight-node data vortex interconnection network subsytem. B. Small, A. Shacham, K. Bergman, K. Athikulwongse, C. Hawkins, and D.S. Will. Journal of Optical Networking Vol. 3, No.11, pp 802-809, November 2004. pdf
  • ChipLock: Support for Secure Microarchitectures. T. Kgil, L Falk, and T. Mudge. Proc. Workshop on Architectural Support for Security and Anti-virus (WASSA), October 2004, pp. 130-139. pdf
  • Design and Applications of a Virtual Context Architecture. D. Oehmke, N. Binkert, S. Reinhardt, and T. Mudge. University of Michigan Technical Report CSE-TR-497-04, September 2004. pdf
  • The Performance Potential of an Integrated Network Interface. N. L. Binkert, R. G. Dreslinski, E. G. Hallnor, L. R. Hsu, S. E. Raasch, A. L. Schultz, and S. K. Reinhardt. Proc. Advanced Networking and Communications Hardware Workshop (ANCHOR), June 2004. pdf
  • A Co-Phase Matrix to Guide Simultaneous Multithreading Simulation. M. Van Biesbrouck, T. Sherwood, and B. Calder. IEEE International Symposium on Performance Analysis and Software (ISPASS), March 2004. pdf
  • A Compressed Memory Hierarchy using an Indirect Index Cache. E. G. Hallnor and S. K. Reinhardt. Proc. 3rd Workshop on Memory Performance Issues (WMPI), June 2004. pdf
    • An extended version appears as University of Michigan Technical Report CSE-TR-488-04, March 2004. pdf

2003

  • The Impact of Resource Partitioning on SMT Processors. S. E. Raasch and S. K. Reinhardt. Proc. 12th Int'l Conf. on Parallel Architectures and Compilation Techniques (PACT), pp. 15-25, Sept. 2003. pdf
  • Network-Oriented Full-System Simulation using M5. N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt. Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2003. pdf
  • Design, Implementation and Use of the MIRV Experimental Compiler for Computer Architecture Research. D. A. Greene. Dissertation at the Universtiy of Michigan, 2003. ">pdf

2002

  • A Scalable Instruction Queue Design Using Dependence Chains. S. E. Raasch, N. L. Binkert, and S. K. Reinhardt. Proc. 29th Annual Int'l Symp. on Computer Architecture (ISCA), pp. 318-329, May 2002. pdf ps ps.gz
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