Difference between revisions of "X86 microop ISA"
From gem5
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| − | + | == Register Ops == | |
| − | + | === Addition and subtraction === | |
| − | + | ==== Add ==== | |
| + | |||
| + | ==== Adc ==== | ||
| + | |||
| + | ==== Sub ==== | ||
| + | |||
| + | ==== Sbb ==== | ||
| + | |||
| + | === Multiplication and division === | ||
| + | |||
| + | ==== Mul1s ==== | ||
| + | |||
| + | ==== Mul1u ==== | ||
| + | |||
| + | ==== Mulel ==== | ||
| + | |||
| + | ==== Muleh ==== | ||
| + | |||
| + | ==== Div1 ==== | ||
| + | |||
| + | ==== Div2 ==== | ||
| + | |||
| + | ==== Divq ==== | ||
| + | |||
| + | ==== Divr ==== | ||
| + | |||
| + | === Logic === | ||
| + | |||
| + | ==== Or ==== | ||
| + | |||
| + | ==== And ==== | ||
| + | |||
| + | ==== Xor ==== | ||
| + | |||
| + | === Shifts and Rotates === | ||
| + | |||
| + | ==== Sll ==== | ||
| + | |||
| + | ==== Srl ==== | ||
| + | |||
| + | ==== Sra ==== | ||
| + | |||
| + | ==== Ror ==== | ||
| + | |||
| + | ==== Rcr ==== | ||
| + | |||
| + | ==== Rol ==== | ||
| + | |||
| + | ==== Rcl ==== | ||
| + | |||
| + | === Data transfer and conversion === | ||
| + | |||
| + | ==== Mov ==== | ||
| + | |||
| + | ==== Sext ==== | ||
| + | |||
| + | ==== Zext ==== | ||
| + | |||
| + | ==== Ruflag ==== | ||
| + | |||
| + | ==== Ruflags ==== | ||
| + | |||
| + | ==== Wruflags ==== | ||
| + | |||
| + | === Control transfer === | ||
| + | |||
| + | ==== Br ==== | ||
| + | |||
| + | ==== Rdip ==== | ||
| + | |||
| + | ==== Wrip ==== | ||
| + | |||
| + | == Load/Store Ops == | ||
| + | |||
| + | == Load immediate Op == | ||
