Revision as of 16:23, 27 September 2007 (view source) Gblack (talk | contribs) (→‎Register Ops) ← Older edit		Revision as of 16:34, 27 September 2007 (view source) Gblack (talk | contribs) (→‎Register Ops) Newer edit →
Line 174:		Line 174:
	== Div1 ==		== Div1 ==
		+
		+	=== div1 ===
		+	Quotient * Src2 + Remainder = Src1
		+	Divisor = Src2
		+
		+	Begins a division operation where the contents of SrcReg1 is the high part of the dividend and the contents of SrcReg2 is the divisor. The remainder from this partial division is put in the internal register Remainder. The quotient is put in the internal register Quotient. The divisor is put in the internal register Divisor.
		+
		+	=== div1i: Quotient * Src1 + Remainder = Src1 ===
		+	Quotient * Imm + Remainder = Src1
		+	Divisor = Imm
		+
		+	Begins a division operation where the contents of SrcReg1 is the high part of the dividend and the immediate Imm is the divisor. The remainder from this partial division is put in the internal register Remainder. The quotient is put in the internal register Quotient. The divisor is put in the internal register Divisor.
		+
		+	=== Flags ===
		+	This microop does not set any flags.
	== Div2 ==		== Div2 ==

---

Revision as of 16:34, 27 September 2007

Register Ops

Add

add: Dest = Src1 + Src2

Adds the contents of the Src1 and Src2 registers and puts the result in the Dest register.

addi: Dest = Src1 + Imm

Adds the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF	The carry out of the most significant bit.
ZF and EZF	Whether the result was zero.
PF	The parity of the result.
AF	The carry from the 4th to 5th bit positions.
SF	The sign of the result.
OF	Whether there was an overflow.

Adc

adc: Dest = Src1 + Src2 + CF

Adds the contents of the Src1 and Src2 registers and the carry flag and puts the result in the Dest register.

adci: Dest = Src1 + Imm + CF

Adds the contents of the Src1 register, the immediate Imm, and the carry flag and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF	The carry out of the most significant bit.
ZF and EZF	Whether the result was zero.
PF	The parity of the result.
AF	The carry from the 4th to 5th bit positions.
SF	The sign of the result.
OF	Whether there was an overflow.

Sub

sub: Dest = Src1 - Src2

Subtracts the contents of the Src2 register from the Src1 register and puts the result in the Dest register.

subi: Dest = Src1 - Imm

Subtracts the contents of the immediate Imm from the Src1 register and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF	The barrow into of the most significant bit.
ZF and EZF	Whether the result was zero.
PF	The parity of the result.
AF	The barrow from the 5th to 4th bit positions.
SF	The sign of the result.
OF	Whether there was an overflow.

Sbb

sbb: Dest = Src1 - Src2 - CF

Subtracts the contents of the Src2 register and the carry flag from the Src1 register and puts the result in the Dest register.

sbbi: Dest = Src1 - Imm - CF

Subtracts the immediate Imm and the carry flag from the Src1 register and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF	The barrow into of the most significant bit.
ZF and EZF	Whether the result was zero.
PF	The parity of the result.
AF	The barrow from the 5th to 4th bit positions.
SF	The sign of the result.
OF	Whether there was an overflow.

Mul1s

mul1s: ProdHi:ProdLo = Src1 * Src2

Multiplies the unsigned contents of the Src1 and Src2 registers and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.

mul1si: ProdHi:ProdLo = Src1 * Imm

Multiplies the unsigned contents of the Src1 register and the immediate Imm and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.

Flags

This microop does not set any flags.

Mul1u

mul1u: ProdHi:ProdLo = Src1 * Src2

Multiplies the unsigned contents of the Src1 and Src2 registers and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.

mul1ui: ProdHi:ProdLo = Src1 * Imm

Multiplies the unsigned contents of the Src1 register and the immediate Imm and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.

Flags

This microop does not set any flags.

Mulel

mulel: Dest = ProdLo

Moves the value of the internal ProdLo register into the Dest register.

Flags

This microop does not set any flags.

Muleh

muleh: Dest = ProdHi

Moves the value of the internal ProdHi register into the Dest register.

Flags

This microop optionally sets the CF, ECF, and OF flags.

CF and ECF	Whether ProdHi is non-zero
OF	Whether ProdHi is non-zero.

Div1

div1

Quotient * Src2 + Remainder = Src1 Divisor = Src2

Begins a division operation where the contents of SrcReg1 is the high part of the dividend and the contents of SrcReg2 is the divisor. The remainder from this partial division is put in the internal register Remainder. The quotient is put in the internal register Quotient. The divisor is put in the internal register Divisor.

div1i: Quotient * Src1 + Remainder = Src1

Quotient * Imm + Remainder = Src1 Divisor = Imm

Begins a division operation where the contents of SrcReg1 is the high part of the dividend and the immediate Imm is the divisor. The remainder from this partial division is put in the internal register Remainder. The quotient is put in the internal register Quotient. The divisor is put in the internal register Divisor.

Flags

This microop does not set any flags.

Div2

Divq

Divr

Or

And

Xor

Sll

Srl

Sra

Ror

Rcr

Rol

Rcl

Mov

Sext

Zext

Ruflag

Ruflags

Wruflags

Br

Rdip

Wrip

Load/Store Ops

Load immediate Op