Difference between revisions of "Status Matrix"
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Revision as of 09:29, 19 September 2011
The follow six tables describe the current state of component combinations in gem5.
Contents
Color Key
| Definitely does not work |
| Might work |
| Should work |
| Definitely works |
| Unknown |
Notes
Numbers in the squares below refer to the following notes:
- Ruby does not support atomic-mode accesses
- The MI_example protocol cannot support LL/SC semantics
- Ruby does not support probing the O3 LSQ to enforce non-weak consistency models
- ARM MP does not support booting with caches, but works otherwise. You can boot without caches then switch to running with caches using either a checkpoint/resume or on-line CPU switchover.
- Classic caches do not support x86 locked (atomic RMW) accesses. The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.
ISA Support Matrices
Alpha
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | Note 2 | |||||||
| FS | uni | |||||||
| multi | Note 2 | |||||||
| InOrder | SE | uni | ||||||
| multi | Note 2 | |||||||
| FS | uni | |||||||
| multi | Note 2 | |||||||
| O3 | SE | uni | ||||||
| multi | Note 2 | Note 3 | Note 3 | Note 3 | Note 3 | |||
| FS | uni | |||||||
| multi | Note 2 | Note 3 | Note 3 | Note 3 | Note 3 | |||
x86
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | Note 5 | |||||||
| FS | uni | Note 5 | ||||||
| multi | Note 5 | |||||||
| InOrder | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| O3 | SE | uni | ||||||
| multi | Note 5 | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | ||
| FS | uni | Note 5 | ||||||
| multi | Note 5 | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | ||
ARM
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | Note 2 | |||||||
| FS | uni | |||||||
| multi | Note 2 | |||||||
| InOrder | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| O3 | SE | uni | ||||||
| multi | Note 2 | Note 3 | Note 3 | Note 3 | Note 3 | |||
| FS | uni | |||||||
| multi | Note 2 | Note 3 | Note 3 | Note 3 | Note 3 | |||
SPARC
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| InOrder | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| O3 | SE | uni | ||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
| FS | uni | |||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
PowerPC
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| InOrder | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| O3 | SE | uni | ||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
| FS | uni | |||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
MIPS
| Processor | Memory System | |||||||
|---|---|---|---|---|---|---|---|---|
| Model | System | Count | Classic | Ruby | ||||
| MI_example | MOESI_hammer | MESI_CMP_directory | MOESI_CMP_directory | MOESI_CMP_token | ||||
| AtomicSimple | SE | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| FS | uni | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | ||
| multi | Note 1 | Note 1 | Note 1 | Note 1 | Note 1 | |||
| TimingSimple | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| InOrder | SE | uni | ||||||
| multi | ||||||||
| FS | uni | |||||||
| multi | ||||||||
| O3 | SE | uni | ||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
| FS | uni | |||||||
| multi | Note 3 | Note 3 | Note 3 | Note 3 | Note 3 | |||
