Difference between revisions of "X86 microop ISA"

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(New page: ==== Register Ops ==== === Addition and subtraction === == Add == == Adc == == Sub == == Sbb == === Multiplication and division === == Mul1s == == Mul1u == == Mulel == == Muleh =...)
 
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==== Register Ops ====
+
[[Register Ops (X86 Microops)|Register Ops]]
  
=== Addition and subtraction ===
+
[[Load/Store Ops (X86 Microops)|Load/Store Ops]]
  
== Add ==
+
[[Load immediate Op (x86 Microops)|Load immediate Op]]
 
 
== Adc ==
 
 
 
== Sub ==
 
 
 
== Sbb ==
 
 
 
=== Multiplication and division ===
 
 
 
== Mul1s ==
 
 
 
== Mul1u ==
 
 
 
== Mulel ==
 
 
 
== Muleh ==
 
 
 
== Div1 ==
 
 
 
== Div2 ==
 
 
 
== Divq ==
 
 
 
== Divr ==
 
 
 
=== Logic ===
 
 
 
== Or ==
 
 
 
== And ==
 
 
 
== Xor ==
 
 
 
=== Shifts and Rotates ===
 
 
 
== Sll ==
 
 
 
== Srl ==
 
 
 
== Sra ==
 
 
 
== Ror ==
 
 
 
== Rcr ==
 
 
 
== Rol ==
 
 
 
== Rcl ==
 
 
 
=== Data transfer and conversion ===
 
 
 
== Mov ==
 
 
 
== Sext ==
 
 
 
== Zext ==
 
 
 
== Ruflag ==
 
 
 
== Ruflags ==
 
 
 
== Wruflags ==
 
 
 
=== Control transfer ===
 
 
 
== Br ==
 
 
 
== Rdip ==
 
 
 
== Wrip ==
 

Revision as of 15:24, 27 September 2007

Register Ops

Load/Store Ops

Load immediate Op