Difference between revisions of "CPU Models"
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==Interfaces== | ==Interfaces== | ||
* [[ThreadContext]] - The ThreadContext class. Used to provide an interface for objects outside of the CPU to access the specific thread state. | * [[ThreadContext]] - The ThreadContext class. Used to provide an interface for objects outside of the CPU to access the specific thread state. | ||
| − | * [[ExecContext]] - The ExecContext interface. An implicit interface that is used by the ISA in order to access the CPU's architected state. | + | * [[Execution_Basics#ExecContext|ExecContext]] - The ExecContext interface. An implicit interface that is used by the ISA in order to access the CPU's architected state. |
==Miscellaneous== | ==Miscellaneous== | ||
* [[Register Indexing]] - How the CPU models keep track of register indices between RISC and CISC ISAs. | * [[Register Indexing]] - How the CPU models keep track of register indices between RISC and CISC ISAs. | ||
Latest revision as of 19:36, 5 July 2011
- SimpleCPU - A good place to start learning about how to fetch, decode, execute, and complete instructions in M5.
- O3CPU - Specific documentation on how all of the pipeline stages work, and how to modify and create new CPU models based on it.
- Checker - Details how to use it in your CPU model.
- InOrderCPU - Specific documentation on how all of the pipeline stages work, and how to modify and create new CPU models based on it.
Supporting classes
- StaticInst - Used to hold static information and methods about specific binary instructions, such as addq's or subq's.
- DynInst - Used to hold dynamic information about instructions in the pipeline, such as the PC or predicted target.
- ThreadState - Used to store thread information that is generic across CPU models.
- SimpleThread - Used by simple CPU models to store architected state and provide the ThreadContext interface.
Interfaces
- ThreadContext - The ThreadContext class. Used to provide an interface for objects outside of the CPU to access the specific thread state.
- ExecContext - The ExecContext interface. An implicit interface that is used by the ISA in order to access the CPU's architected state.
Miscellaneous
- Register Indexing - How the CPU models keep track of register indices between RISC and CISC ISAs.
