Difference between revisions of "User workshop 2012"
From gem5
| Line 26: | Line 26: | ||
| Introduction || style="text-align:right"|8:30 AM || Ali Saidi || ARM | | Introduction || style="text-align:right"|8:30 AM || Ali Saidi || ARM | ||
|- | |- | ||
| − | | Recent Contributions | + | | colspan="4" align="center" style="background:lightgreen" | Recent Contributions |
|- | |- | ||
| Memory System Enhancements || style="text-align:right"|8:45 AM || Andreas Hannson || ARM | | Memory System Enhancements || style="text-align:right"|8:45 AM || Andreas Hannson || ARM | ||
| Line 32: | Line 32: | ||
| Visualizing stats via Streamline || style="text-align:right"|9:05 AM || Dam Sunwoo || ARM | | Visualizing stats via Streamline || style="text-align:right"|9:05 AM || Dam Sunwoo || ARM | ||
|- | |- | ||
| − | | User Perspectives | + | | colspan="4" align="center" style="background:lightgreen" | User Perspectives |
|- | |- | ||
| HAsim: FPGA-Based Micro-Architecture Simulator || style="text-align:right"|9:20 AM || Michael Adler || Intel | | HAsim: FPGA-Based Micro-Architecture Simulator || style="text-align:right"|9:20 AM || Michael Adler || Intel | ||
| Line 39: | Line 39: | ||
|- | |- | ||
| Eclipse Integration || style="text-align:right"|9:50 AM || Deyuan Guo and Hu He || Tsinghua Univ. | | Eclipse Integration || style="text-align:right"|9:50 AM || Deyuan Guo and Hu He || Tsinghua Univ. | ||
| − | |- | + | |- style="background:lightgray" |
| Break || style="text-align:right"|10:05 AM || || | | Break || style="text-align:right"|10:05 AM || || | ||
|- | |- | ||
| Line 53: | Line 53: | ||
|- | |- | ||
| Cross-Cutting Infrastructure for Evaluating Managed Architectures and Future Languages || style="text-align:right"|11:45 AM || Paul Gratz || Texas A&M Univ. | | Cross-Cutting Infrastructure for Evaluating Managed Architectures and Future Languages || style="text-align:right"|11:45 AM || Paul Gratz || Texas A&M Univ. | ||
| − | |- | + | |- style="background:lightgray" |
| Lunch || style="text-align:right"|12:00 PM || || | | Lunch || style="text-align:right"|12:00 PM || || | ||
|- | |- | ||
| Line 62: | Line 62: | ||
| gem5-fusion: A Simulator for Heterogeneous Processors || style="text-align:right"|1:30 PM || Jason Power and Marc Orr || Univ. of Wisconsin-Madison | | gem5-fusion: A Simulator for Heterogeneous Processors || style="text-align:right"|1:30 PM || Jason Power and Marc Orr || Univ. of Wisconsin-Madison | ||
|- | |- | ||
| − | | | + | | colspan="4" align="center" style="background:lightgreen" | Breakout Sessions |
|- | |- | ||
| + | | Breakout Sessions || style="text-align:right"|1:45 PM || Breakout Groups || | ||
| + | |- style="background:lightgray" | ||
| Break || style="text-align:right"|3:00 PM || || | | Break || style="text-align:right"|3:00 PM || || | ||
|- | |- | ||
| − | | Wrap-Up/ | + | | Wrap-Up/Next Steps || style="text-align:right"|3:30 PM || Everyone || |
| + | |- | ||
| + | | colspan="4" align="center" | | ||
|- | |- | ||
| Conclusions || style="text-align:right"|4:00 PM || Steve Reinhardt || AMD | | Conclusions || style="text-align:right"|4:00 PM || Steve Reinhardt || AMD | ||
Revision as of 16:56, 26 November 2012
|
The primary objective of this workshop is to bring together groups across the community
who are actively using gem5, discuss what is going on in the gem5
community, how we can best leverage each others contributions, and how
we continue to make gem5 a successful community-supported simulation
framework. Those who will get the most out of the conference are
current users of gem5, although anyone is welcome to attend.
Program
| Topic | Time | Presenter | Affiliation |
|---|---|---|---|
| Introduction | 8:30 AM | Ali Saidi | ARM |
| Recent Contributions | |||
| Memory System Enhancements | 8:45 AM | Andreas Hannson | ARM |
| Visualizing stats via Streamline | 9:05 AM | Dam Sunwoo | ARM |
| User Perspectives | |||
| HAsim: FPGA-Based Micro-Architecture Simulator | 9:20 AM | Michael Adler | Intel |
| VLIW DSPs/MIPS FS mode | 9:35 AM | Deyuan Guo and Hu He | Tsinghua Univ. |
| Eclipse Integration | 9:50 AM | Deyuan Guo and Hu He | Tsinghua Univ. |
| Break | 10:05 AM | ||
| Full-System Workloads and Asymmetric Multi-Core Simulation | 10:30 AM | Anthony Gutierrez | Univ. of Michigan |
| ARM SoC exploration | 10:45 AM | Alexandre Romana and Abhilash Nair | Texas Instruments |
| SystemC integration | 11:00 AM | Alexandre Romana and Abhilash Nair | Texas Instruments |
| Composite Cores | 11:15 AM | Shruti Padmanabha and Andrew Lukefahr | Univ. of Michigan |
| Customized InOrder CPU Modeling | 11:30 AM | Korey Sewell | Univ. of Michigan (now at Qualcomm) |
| Cross-Cutting Infrastructure for Evaluating Managed Architectures and Future Languages | 11:45 AM | Paul Gratz | Texas A&M Univ. |
| Lunch | 12:00 PM | ||
| Simplifying SLICC via Atomic Messages | 1:00 PM | Brad Beckmann | AMD |
| Accelerating Simulation with Virtual Machines | 1:15 PM | Ali Saidi | ARM |
| gem5-fusion: A Simulator for Heterogeneous Processors | 1:30 PM | Jason Power and Marc Orr | Univ. of Wisconsin-Madison |
| Breakout Sessions | |||
| Breakout Sessions | 1:45 PM | Breakout Groups | |
| Break | 3:00 PM | ||
| Wrap-Up/Next Steps | 3:30 PM | Everyone | |
| Conclusions | 4:00 PM | Steve Reinhardt | AMD |
Location
The workshop is co-located with MICRO-45 in Vancouver, BC.
Date
Sunday December 2nd from 8:30 - 16:30.
