Difference between revisions of "Tutorials"
(→ISCA 45: AMD gem5 APU Model) |
(→ISCA 45: AMD gem5 APU Model) |
||
| Line 16: | Line 16: | ||
* [http://gem5.org/dist/tutorials/hipeac2012/09.configuration.m4v Configuration] | * [http://gem5.org/dist/tutorials/hipeac2012/09.configuration.m4v Configuration] | ||
* [http://gem5.org/dist/tutorials/hipeac2012/10.conclusions.m4v Conclusion] | * [http://gem5.org/dist/tutorials/hipeac2012/10.conclusions.m4v Conclusion] | ||
| + | |||
| + | == ICS 2018: Vector Architecture Exploration with gem5== | ||
| + | [http://gem5.org/ICS2018_gem5_SVE_Tutorial Vector Architecture Exploration with gem5] | ||
| + | |||
| + | Internationcal Conference on Supercomputing, Beijing (China), June 2018 | ||
| + | |||
| + | This tutorial covers the Arm Scalable Vector Extension (SVE) and how to use gem5 to explore system architecture designs of microarchitectures implementing SVE. | ||
| + | |||
== ISCA 45: AMD gem5 APU Model == | == ISCA 45: AMD gem5 APU Model == | ||
Revision as of 14:58, 22 February 2018
We have held a handful of tutorials on M5 at various conferences. Though the material in these tutorials can be out of date, the tutorial materials present a more organized (and in some cases more in-depth) overview than the wiki documentation. We highly recommend taking a look at the most recent tutorial as a complement to the documentation on the wiki.
The slides and handouts are the same material except that the handouts are formatted with two slides per page.
Contents
HiPEAC Computer Systems Week
This tutorial was held in Gothenburg, Sweden in April 2012. It covers gem5 although for information about Ruby you should look at the ISCA 38 tutorial. We recorded video of the tutorial which is available below.
- Slides
- Overview
- Introduction
- Basics
- Running Experiments
- Debugging
- Memory
- CPU Models
- Common Tasks
- Configuration
- Conclusion
ICS 2018: Vector Architecture Exploration with gem5
Vector Architecture Exploration with gem5
Internationcal Conference on Supercomputing, Beijing (China), June 2018
This tutorial covers the Arm Scalable Vector Extension (SVE) and how to use gem5 to explore system architecture designs of microarchitectures implementing SVE.
ISCA 45: AMD gem5 APU Model
AMD gem5 APU Simulator: Modeling GPUs Using the Machine ISA
This tutorial covers the gem5 APU model in detail. In particular, we discuss the model's support for executing GPU machine ISA instructions and the full user space ROCm stack.
Arm Research Summit 2017: gem5 workshop
ARM Research Summit 2017 Workshop covers many advanced topics in gem5 such as Ruby, Garnet, and SystemC.
dist-gem5 at ISCA-44 (Toronto, 2017)
dist-gem5 is a gem5-based simulation infrastructure which enables full-system simulation of a parallel/distributed computer system using multiple simulation hosts.
ASPLOS 22
Full day tutorial on gem5 at ASPLOS 2017
ISCA 38
This tutorial, held in June 2011 at ISCA-38, it covered gem5 (the merger between M5 and GEMS). It was extremely well attended with 65 people participating.
- Slides
- Podcasts/video coming soon provided there are no technical difficulties
ASPLOS-13
This tutorial, held in March 2008 at ASPLOS XIII in Seattle, covered M5 2.0 and included several small examples on creating SimObjects and adding parameters.
- Slides
- Handouts
- Video
- Introduction -- A brief overview of M5, its capabilities and concepts
- Running -- How to compile and run M5
- Full System -- Full system benchmarks, disk images, and scripts
- Objects -- An overview of the various object models that are available out of the box
- Extending -- M5 internals, defining new objects & parameters, statistics, ISA descriptions, ARM & X86 support, future development
- Debugging -- Facilities in M5 to aid debugging
- Description
ISCA-33
This tutorial, held in June 2006 at ISCA 33 in Boston, was the first one to cover M5 2.0.
ISCA-32
Our first tutorial, held in June 2005 at ISCA 32 in Madison, is rather dated as it covered M5 1.X and not 2.0.
