Status Matrix

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The follow six tables describe the current state of component combinations in gem5.

Contents

1 Color Key
2 Notes
3 ISA Support Matrices
- 3.1 Alpha
- 3.2 x86
- 3.3 ARM
- 3.4 SPARC
- 3.5 PowerPC
- 3.6 MIPS

Color Key

Definitely does not work
Might work
Should work
Definitely works
Unknown

Notes

Numbers in the squares below refer to the following notes:

Ruby does not support atomic-mode accesses
The MI_example protocol cannot support LL/SC semantics
Classic caches do not support x86 locked (atomic RMW) accesses. The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.

ISA Support Matrices

Alpha

Processor			Memory System
Model	System	Count	Classic	Ruby
Model	System	Count	Classic	MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	SE	multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
	SE	multi		Note 2
	FS	uni
	FS	multi		Note 2
InOrder	SE	uni
	SE	multi		Note 2
	FS	uni
	FS	multi		Note 2
O3	SE	uni
	SE	multi		Note 2
	FS	uni
	FS	multi		Note 2

x86

Processor			Memory System
Model	System	Count	Classic	Ruby
Model	System	Count	Classic	MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	SE	multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
	SE	multi	Note 3
	FS	uni	Note 3
	FS	multi	Note 3
InOrder	SE	uni
	SE	multi
	FS	uni
	FS	multi
O3	SE	uni
	SE	multi	Note 3	Note 2
	FS	uni	Note 3	Note 2
	FS	multi	Note 3	Note 2

ARM

Processor			Memory System
Model	System	Count	Classic	Ruby
Model	System	Count	Classic	MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	SE	multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
	SE	multi		Note 2
	FS	uni
	FS	multi		Note 2
InOrder	SE	uni
	SE	multi
	FS	uni
	FS	multi
O3	SE	uni
	SE	multi		Note 2
	FS	uni		Note 2
	FS	multi		Note 2

SPARC

Processor			Memory System
Model	System	Count	Classic	Ruby
Model	System	Count	Classic	MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	SE	multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
	SE	multi
	FS	uni
	FS	multi
InOrder	SE	uni
	SE	multi
	FS	uni
	FS	multi
O3	SE	uni
	SE	multi		Note 2
	FS	uni
	FS	multi		Note 2

PowerPC

Processor			Memory System
Model	System	Count	Classic	Ruby
Model	System	Count	Classic	MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	SE	multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
	SE	multi
	FS	uni
	FS	multi
InOrder	SE	uni
	SE	multi
	FS	uni
	FS	multi
O3	SE	uni
	SE	multi		Note 3	Note 3	Note 3	Note 3	Note 3
	FS	uni
	FS	multi		Note 3	Note 3	Note 3	Note 3	Note 3

MIPS

Processor			Memory System
Model	System	Count	Classic	Ruby
Model	System	Count	Classic	MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	SE	multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
	SE	multi
	FS	uni
	FS	multi
InOrder	SE	uni
	SE	multi
	FS	uni
	FS	multi
O3	SE	uni
	SE	multi		Note 3	Note 3	Note 3	Note 3	Note 3
	FS	uni
	FS	multi		Note 3	Note 3	Note 3	Note 3	Note 3

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