Defining ISAs (as of M5 2.0 beta 3)

• NOTE: THIS PAGE IS UNDER CONSTRUCTION. HOPE TO FINISH SOON!!!

Overview

First, make sure you have basic understanding of how an ISA description generates instructions within the M5 framework. A good start is the The M5 ISA description language page.

For this example, we will be constructing an ISA called MyISA which will just be a renamed version of the MIPS ISA. We will go through the steps of creating the files and configuration opions for an M5 ISA description.

Your new ISA description, MyISA, will need to generate correct instructions for the different CPU models. More specifically, your MyISA description will allow your MyISA architecture (analagous to ALPHA,MIPS,SPARC,etc.) to be plugged into System-Call Emulation (SE) and Full-System (FS) simulations of any M5 CPU Model.

Syscall Emulation (SE) Mode MyISA

MyISA Decoder - src/arch/MyISA/decoder.isa

Now Build Your Decoder:

scons build/MYISA_SE/arch/MyISA/atomic_simple_cpu_exec.cc CPU_MODELS=AtomicSimpleCPU