X86 microop ISA
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Revision as of 14:30, 27 September 2007 by
Gblack
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Contents
1
Register Ops
1.1
Addition and subtraction
1.1.1
Add
1.1.2
Adc
1.1.3
Sub
1.1.4
Sbb
1.2
Multiplication and division
1.2.1
Mul1s
1.2.2
Mul1u
1.2.3
Mulel
1.2.4
Muleh
1.2.5
Div1
1.2.6
Div2
1.2.7
Divq
1.2.8
Divr
1.3
Logic
1.3.1
Or
1.3.2
And
1.3.3
Xor
1.4
Shifts and Rotates
1.4.1
Sll
1.4.2
Srl
1.4.3
Sra
1.4.4
Ror
1.4.5
Rcr
1.4.6
Rol
1.4.7
Rcl
1.5
Data transfer and conversion
1.5.1
Mov
1.5.2
Sext
1.5.3
Zext
1.5.4
Ruflag
1.5.5
Ruflags
1.5.6
Wruflags
1.6
Control transfer
1.6.1
Br
1.6.2
Rdip
1.6.3
Wrip
2
Load/Store Ops
3
Load immediate Op
Register Ops
Addition and subtraction
Add
Adc
Sub
Sbb
Multiplication and division
Mul1s
Mul1u
Mulel
Muleh
Div1
Div2
Divq
Divr
Logic
Or
And
Xor
Shifts and Rotates
Sll
Srl
Sra
Ror
Rcr
Rol
Rcl
Data transfer and conversion
Mov
Sext
Zext
Ruflag
Ruflags
Wruflags
Control transfer
Br
Rdip
Wrip
Load/Store Ops
Load immediate Op
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