X86 microop ISA

From gem5
Revision as of 14:54, 27 September 2007 by Gblack (talk | contribs)
Jump to: navigation, search

Register Ops

Add

add: Dest = Src1 + Src2

Adds the contents of the Src1 and Src2 registers and puts the result in the Dest register.

addi: Dest = Src1 + Imm

Adds the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.

Flags

This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.

CF and ECF The carry out of the most significant bit.
ZF and EZF Whether the result was zero.
PF The parity of the result.
AF The carry from the 4th to 5th bit positions.
SF The sign of the result.
OF Whether there was an overflow.

Adc

Sub

Sbb

Multiplication and division

Mul1s

Mul1u

Mulel

Muleh

Div1

Div2

Divq

Divr

Logic

Or

And

Xor

Shifts and Rotates

Sll

Srl

Sra

Ror

Rcr

Rol

Rcl

Data transfer and conversion

Mov

Sext

Zext

Ruflag

Ruflags

Wruflags

Control transfer

Br

Rdip

Wrip

Load/Store Ops

Load immediate Op