Google Summer of Code

Introduction

The Google Summer of Code (SoC) is a great opportunity for students to contribute to open source software projects. The open source projects get additional contributions and active developers while the students get some money and gain experience in large distributed software development.

About M5

M5 is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture. At its core M5 provides a generic, object-oriented discrete-event simulation framework. This includes a foundation for: defining, parameterizing, configuring, and marshaling simulation objects. The foundation along with various pre-made object models allow M5 simulate both single systems and multiple networked systems deterministically. Simulations can be run using one binary (syscall emulation) or booting an entire operating system such as Linux or Solaris (full-system) on most major ISAs (SPARC, MIPS, ALPHA, ARM, x86/64). The simulator is written in a combination of C++ and Python and is pervasively object oriented. Python is used for configuration and not-performance critical parts, while C++ is used for the core of the simulation framework. Using the M5 simulator, computer architecture researchers around the world have been able to successfully model their systems and publish their work in magazines, conferences, and academic journals. So far, the Publications list has reached more than 50 and it grows every year.

Project Ideas

Below is a list of possible project ideas and starting points, however we're open to other ideas students may have. All the ideas listed here will require some familiarity with Python and a good grasp of advanced C++ concepts.

Direct Execution model

1. Build a direct execution CPU model based on the Linux Kernel Virtual Machine
   • http://kvm.qumranet.com/kvmwiki

Parallelization

1. Parallelize M5
   • Use the Wisconsin Wind Tunnel as a guide
   • This actually isn't as bad as it sounds as all objects schedule their own events and there are limited ways they can interact with other objects in the system.

Memory Network Models

1. Memory network models
   • (e.g. Crossbar or Mesh)

Directory Coherence Protocol

1. Directory Protocol

Detailed In-Order core model

1. Real In-order core model
   • There is code to start with but nothing that is fully fleshed out.

Interface to an HDL

1. Write a PLI interface to connect Verilog CPUs to the memory system.

Sampling/fast-forwarding techniques

1. Sampling/fast-forwarding techniques
   • This would have the most impact if it was coupled with (1)
   • Using SMARTS work would be a good guide

Other device models

1. Flash memory device model (seems popular nowadays)
   • This could be a hard drive based model like we're seeing in laptops now or a memory device model like several research papers have suggested as storage in between DRAM and disk.

Other

Here is some idea of how we would expect the project to be carried out:

• Make M5 your main summer activity and set milestones for your project. This will assist the mentors and yourself in tracking your progress and will allow you to schedule breaks from your summer software development accordingly.

• Use the M5 Mailing Lists so that you can keep your work open and into the community. Asking a question or posting a response to the list allows for everyone to be involved in solving problems and developing quality software quickly.

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Mentors / M5 Simulation Team

• Steve Reinhardt - Simulator Infrastructure; Parallel Simulation; ISA description; Full System Simulation; Memory Modeling
• Nate Binkert - Simulator Infrastructure; Parallel Simulation; Python Integration; Full System Simulation; Networking Models; Configuration Scripts
• Ali Saidi - Networking Models; Device Modeling; Full System Simulation; Memory Modeling not including caches
• Lisa Hsu - Full System Workloads; Memory Modeling; Checkpointing Simulations
• Kevin Lim - CPU Modeling (Out-of-Order, SimpleCPU) ; Full-System Simulation;
• Gabe Black - ISA description (SPARC, x86); Full System Simulation
• Korey Sewell - ISA description (MIPS); Out-of-Order CPU Modeling; SMT Simulation
• Ron Dreslinski - Memory Modeling