InOrder Pipeline Stages
From gem5
Contents
Overview
Relevant source files:
- first_stage.[hh,cc]
- pipeline_stage.[hh,cc]
- pipeline_traits.[hh,cc]
- cpu.[hh,cc]
Interstage Communication
Pipeline Processing
First Stage
Implementations
In it's most basic incarnation, the In-Order model models a 5-stage pipeline.
The 5-stage pipeline is based on the 5-stage MIPS pipeline and has the following stages:
- Instruction Fetch (IF)
- Instruction Decode (ID)
- Execute (EX)
- Memory Access (MEM)
- Register Write Back (WB)
Pipeline Customization
Stage Instantiation
Adding Your Own Stage
- Python Configuration
- Instruction Schedule Information
