Status Matrix

The follow six tables describe the current state of component combinations in gem5.

Color Key

Definitely does not work

Might work

Should work

Definitely works

Unknown

Notes

Below Classic and Ruby refers to the two memory systems that we have in gem5. MI, MESI and MOESI (multiple flavors) are the coherence protocols that are supported in Ruby memory system. Then we have the CPU models: AtomicSimple, TimingSimple, InOrder and O3.

Numbers in the squares below refer to the following notes:

1. Ruby does not support atomic-mode accesses
2. The MI_example protocol cannot support LL/SC semantics
3. Classic caches do not support x86 locked (atomic RMW) accesses. The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.

ISA Support Matrices

Alpha

Processor			Memory System
Model	System	Count	Classic	Ruby
				MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
		multi		Note 2
	FS	uni
		multi		Note 2
InOrder	SE	uni
		multi		Note 2
	FS	uni
		multi		Note 2
O3	SE	uni
		multi		Note 2
	FS	uni
		multi		Note 2

ARM

Processor			Memory System
Model	System	Count	Classic	Ruby
				MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
		multi		Note 2
	FS	uni
		multi		Note 2
InOrder	SE	uni
		multi
	FS	uni
		multi
O3	SE	uni
		multi		Note 2
	FS	uni		Note 2
		multi		Note 2

x86

Processor			Memory System
Model	System	Count	Classic	Ruby
				MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
		multi	Note 3
	FS	uni	Note 3
		multi	Note 3
InOrder	SE	uni
		multi
	FS	uni
		multi
O3	SE	uni
		multi	Note 3	Note 2
	FS	uni	Note 3	Note 2
		multi	Note 3	Note 2

SPARC

Processor			Memory System
Model	System	Count	Classic	Ruby
				MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
		multi
	FS	uni
		multi
InOrder	SE	uni
		multi
	FS	uni
		multi
O3	SE	uni
		multi		Note 2
	FS	uni
		multi		Note 2

PowerPC

Processor			Memory System
Model	System	Count	Classic	Ruby
				MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
		multi
	FS	uni
		multi
InOrder	SE	uni
		multi
	FS	uni
		multi
O3	SE	uni
		multi		Note 2
	FS	uni
		multi		Note 2

MIPS

Processor			Memory System
Model	System	Count	Classic	Ruby
				MI_example	MOESI_hammer	MESI_CMP_directory	MOESI_CMP_directory	MOESI_CMP_token
AtomicSimple	SE	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
	FS	uni		Note 1	Note 1	Note 1	Note 1	Note 1
		multi		Note 1	Note 1	Note 1	Note 1	Note 1
TimingSimple	SE	uni
		multi
	FS	uni
		multi
InOrder	SE	uni
		multi
	FS	uni
		multi
O3	SE	uni
		multi		Note 2
	FS	uni
		multi		Note 2