Difference between revisions of "User workshop 2012"
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| − | <div style="font-size:202%;border:none;margin: 0;padding:.3em;text-align:center;color:#000">First | + | <div style="font-size:202%;border:none;margin: 0;padding:.3em;text-align:center;color:#000">First gem5 User Workshop</div> |
<div style="font-size:140%;border:none;margin: 0;padding:.3em;text-align:center;color:#000">December 2012; Vancouver, BC</div> | <div style="font-size:140%;border:none;margin: 0;padding:.3em;text-align:center;color:#000">December 2012; Vancouver, BC</div> | ||
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| [[Media:201212 HAsim GEM5.pdf|HAsim: FPGA-Based Micro-Architecture Simulator]] || style="text-align:right"|9:20 AM || Michael Adler || Intel | | [[Media:201212 HAsim GEM5.pdf|HAsim: FPGA-Based Micro-Architecture Simulator]] || style="text-align:right"|9:20 AM || Michael Adler || Intel | ||
|- | |- | ||
| − | | VLIW DSPs/MIPS FS mode || style="text-align:right"|9:35 AM || Deyuan Guo and Hu He || Tsinghua Univ. | + | | [[Media:Tsinghua's Presentation for gem5 Workshop 2012.pdf|VLIW DSPs/MIPS FS mode]] || style="text-align:right"|9:35 AM || Deyuan Guo and Hu He || Tsinghua Univ. |
|- | |- | ||
| − | | Eclipse Integration || style="text-align:right"|9:50 AM || Deyuan Guo and Hu He || Tsinghua Univ. | + | | [[Media:Tsinghua's Presentation for gem5 Workshop 2012.pdf|Eclipse Integration]] || style="text-align:right"|9:50 AM || Deyuan Guo and Hu He || Tsinghua Univ. |
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| Break || style="text-align:right"|10:05 AM || || | | Break || style="text-align:right"|10:05 AM || || | ||
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| [[Media:Gutierrez gem5 workshop 2012.pdf|Full-System Workloads and Asymmetric Multi-Core Simulation]] || style="text-align:right"|10:30 AM || Anthony Gutierrez || Univ. of Michigan | | [[Media:Gutierrez gem5 workshop 2012.pdf|Full-System Workloads and Asymmetric Multi-Core Simulation]] || style="text-align:right"|10:30 AM || Anthony Gutierrez || Univ. of Michigan | ||
|- | |- | ||
| − | | ARM SoC exploration || style="text-align:right"|10:45 AM || Alexandre Romana and Abhilash Nair || Texas Instruments | + | | [[Media:Gem5_workshop_arm_soc_exploration_ext.pdf|ARM SoC exploration]] || style="text-align:right"|10:45 AM || Alexandre Romana and Abhilash Nair || Texas Instruments |
|- | |- | ||
| − | | SystemC integration || style="text-align:right"|11:00 AM || Alexandre Romana | + | | [[Media:Gem5_workshop_systemC_integration_ext.pdf|SystemC integration]] || style="text-align:right"|11:00 AM || Alexandre Romana || Texas Instruments |
|- | |- | ||
| − | | Composite Cores || style="text-align:right"|11:15 AM || Shruti Padmanabha and Andrew Lukefahr || Univ. of Michigan | + | | [[Media:Performance Prediction Models gem5 workshop.pdf|Composite Cores]] || style="text-align:right"|11:15 AM || Shruti Padmanabha and Andrew Lukefahr || Univ. of Michigan |
|- | |- | ||
| [[Media:2012 workshop gem5 inorder modeling.pdf|Customized InOrder CPU Modeling]] || style="text-align:right"|11:30 AM || Korey Sewell || Univ. of Michigan (now at Qualcomm) | | [[Media:2012 workshop gem5 inorder modeling.pdf|Customized InOrder CPU Modeling]] || style="text-align:right"|11:30 AM || Korey Sewell || Univ. of Michigan (now at Qualcomm) | ||
|- | |- | ||
| − | | Cross-Cutting Infrastructure for Evaluating Managed Languages and Future Architectures || style="text-align:right"|11:45 AM || Paul Gratz || Texas A&M Univ. | + | | [[Media:2012 gem5 modern languages infrastructure.pdf|Cross-Cutting Infrastructure for Evaluating Managed Languages and Future Architectures]] || style="text-align:right"|11:45 AM || Paul Gratz || Texas A&M Univ. |
|- style="background:lightgray" | |- style="background:lightgray" | ||
| Lunch || style="text-align:right"|12:00 PM || || | | Lunch || style="text-align:right"|12:00 PM || || | ||
|- | |- | ||
| − | | Simplifying SLICC via Atomic Messages || style="text-align:right"|1:00 PM || Brad Beckmann || AMD | + | | [[Media:Atomic interfaces micro 2012 final.pdf|Simplifying SLICC via Atomic Messages]] || style="text-align:right"|1:00 PM || Brad Beckmann || AMD |
|- | |- | ||
| [[Media:2012 12 gem5 workshop kvm.pdf|Accelerating Simulation with Virtual Machines]] || style="text-align:right"|1:15 PM || Ali Saidi || ARM | | [[Media:2012 12 gem5 workshop kvm.pdf|Accelerating Simulation with Virtual Machines]] || style="text-align:right"|1:15 PM || Ali Saidi || ARM | ||
|- | |- | ||
| − | | [[Media:2012 12 gem5 gpu.pdf|gem5- | + | | [[Media:2012 12 gem5 gpu.pdf|gem5-gpu: A Simulator for Heterogeneous Processors]] || style="text-align:right"|1:30 PM || Jason Power and Marc Orr || Univ. of Wisconsin-Madison |
|- | |- | ||
| colspan="4" align="center" style="background:lightgreen" | Breakout Sessions | | colspan="4" align="center" style="background:lightgreen" | Breakout Sessions | ||
Latest revision as of 04:44, 11 February 2015
|
The primary objective of this workshop is to bring together groups across the community
who are actively using gem5, discuss what is going on in the gem5
community, how we can best leverage each others contributions, and how
we continue to make gem5 a successful community-supported simulation
framework. Those who will get the most out of the conference are
current users of gem5, although anyone is welcome to attend.
Program
| Topic | Time | Presenter | Affiliation |
|---|---|---|---|
| Introduction | 8:30 AM | Ali Saidi | ARM |
| Recent Contributions | |||
| Memory System Enhancements | 8:45 AM | Andreas Hannson | ARM |
| Visualizing stats via Streamline | 9:05 AM | Dam Sunwoo | ARM |
| User Perspectives | |||
| HAsim: FPGA-Based Micro-Architecture Simulator | 9:20 AM | Michael Adler | Intel |
| VLIW DSPs/MIPS FS mode | 9:35 AM | Deyuan Guo and Hu He | Tsinghua Univ. |
| Eclipse Integration | 9:50 AM | Deyuan Guo and Hu He | Tsinghua Univ. |
| Break | 10:05 AM | ||
| Full-System Workloads and Asymmetric Multi-Core Simulation | 10:30 AM | Anthony Gutierrez | Univ. of Michigan |
| ARM SoC exploration | 10:45 AM | Alexandre Romana and Abhilash Nair | Texas Instruments |
| SystemC integration | 11:00 AM | Alexandre Romana | Texas Instruments |
| Composite Cores | 11:15 AM | Shruti Padmanabha and Andrew Lukefahr | Univ. of Michigan |
| Customized InOrder CPU Modeling | 11:30 AM | Korey Sewell | Univ. of Michigan (now at Qualcomm) |
| Cross-Cutting Infrastructure for Evaluating Managed Languages and Future Architectures | 11:45 AM | Paul Gratz | Texas A&M Univ. |
| Lunch | 12:00 PM | ||
| Simplifying SLICC via Atomic Messages | 1:00 PM | Brad Beckmann | AMD |
| Accelerating Simulation with Virtual Machines | 1:15 PM | Ali Saidi | ARM |
| gem5-gpu: A Simulator for Heterogeneous Processors | 1:30 PM | Jason Power and Marc Orr | Univ. of Wisconsin-Madison |
| Breakout Sessions | |||
| Breakout Sessions | 1:45 PM | Breakout Groups | |
| Break | 3:00 PM | ||
| Wrap-Up/Next Steps | 3:30 PM | Everyone | |
| Conclusions | 4:00 PM | Steve Reinhardt | AMD |
Location
The workshop is co-located with MICRO-45 in Vancouver, BC.
Date
Sunday December 2nd from 8:30 - 16:30.
